參數(shù)資料
型號(hào): W6692A
英文描述: TE Mode S/T Controller with PCI 2.2 Interface and ACPT
中文描述: TE模S / T的2.2與PCI控制器接口和ACPT
文件頁(yè)數(shù): 56/101頁(yè)
文件大?。?/td> 851K
代理商: W6692A
W6692A
- 56 -
This register masks (disables) the second byte address comparison of the incoming frame. If the
mask bit is "1" the corresponding bit comparisons with D_TEI1, D_TEI2 are disabled. Comparison
with TEIG is always performed.
Note
: For the LAPD frame, the least significant bit is the EA =1 bit.
8.1.16 D_ch TEI1 Register D_TEI1 Read/Write Address 3CH/0FH
Value after reset: 00H
7
6
5
4
3
2
1
0
TA17
TA16
TA15
TA14
TA13
TA12
TA11
TA10
TA17 - TA10
This register contains the first choice of the second byte address of received frame. For LAPD frame,
TA17 - TA11 is the TEI value, TA10 is EA = 1.
8.1.17 D_ch TEI2 Register D_TEI2 Read/Write Address 40H/10H
Value after reset: 00H
7
6
5
4
3
2
1
0
TA27
TA26
TA25
TA24
TA23
TA22
TA21
TA20
TA27 - TA20
This register contains the second choice of the second byte address of received frame. For LAPD
frame, TA27 - TA21 is the TEI value, TA20 is EA = 1.
8.1.18 D_ch Receive Frame Byte Count High D_RBCH Read Address 44H/11H
Value after reset: 40H
7
6
5
4
3
2
1
0
VN1
VN0
LOV
RBC12 RBC11 RBC10
RBC9
RBC8
VN1-0 Chip Version Number
This is the chip version number. It is read as 01B.
LOV Length Overflow
A "1" in this bit indicates
8192 bytes are received and the frame is not yet complete. This bit is valid
only after an D_RME interrupt and remains valid until the frame is acknowledge via the RACK
command.
RBC12-8 Receive Byte Count
Four most significant bits of the total frame length. These bits are valid only after an D_RME interrupt
and remain valid until the frame is acknowledge via the RACK command.
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