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參數(shù)資料
| 型號： | W6692A |
| 英文描述： | TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| 中文描述： | TE模S / T的2.2與PCI控制器接口和ACPT |
| 文件頁數(shù)： | 38/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692A |
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W6692A
- 38 -
- Extended transparent mode
Characteristics :
* All data transmitted/ received without modification
* No address comparison
* No flag generation/ detection
* No FCS generation/ check
* No bit stuffing
For PCM-HDLC connection, only extended transparent mode can be selected.
The data rate in B channel can be set at 64 kbps or 56 kbps by the B1_MODE (B2_MODE): SW56
bit.
7.7.1 Reception of Frames in B Channel
A 128-byte FIFO is provided in the receive direction. The receive FIFO threshold can be set at 64 or
96 bytes by the Bn_MODE register. If the number of received data reaches the threshold, a Receive
Message Ready (RMR) interrupt will be generated.
The operations for reception of frames differ in each mode:
Transparent mode
: The received frame address is compared with the contents in receive address
registers. In addition, the comparisons can be selectively masked bit-by-bit via address mask
registers. Comparison is disabled when the corresponding mask bit is "1".
In addition, flag recognition, CRC check and zero bit deletion are also performed. The result of CRC
check is indicated in Bn_STAR: CRCE bit. The data between opening flag and CRC field (not
included) is stored in receive FIFO. Two interrupts are used for the reception of data. The RMR
interrupt in Bn_EXIR register indicates at least a threshold block of data have been put in the receive
FIFO. The RME interrupt in Bn_EXIR register indicates the end of frame has been received. The
micro-processor can read out a threshold length of data from receive FIFO at RMR interrupt, or all
the data in receive FIFO at RME interrupt. At each RMR/ RME interrupt, micro-processor must issue
a Receive Message Acknowledgement(RACK) command to explicitly acknowledge the interrupt.
The microprocessor reaction time for RMR/ RME interrupt depends on the FIFO threshold setting and
B channel data rate. For example, it is 8 mS if the FIFO threshold is 64 and the B channel data rate is
64 kbps.
If the microprocessor is late in handling the interrupt, the incoming additional bytes will result in a
"data overflow" interrupt and status bit.
Extended transparent mode
: In this mode, all data received are stored in the receive FIFO without
any modification. Every time up to a threshold length of data has been stored in the FIFO, a Bn_RMR
interrupt is generated.
In this mode, there is no RME interrupt.
The microprocessor must react to the RMR interrupt in time, otherwise a "data overflow" interrupt and
status bit will be generated.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W6692ACD | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694A | TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | USB Bus ISDN S/T-Controller |
| W7020 | Telecommunication IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
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