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參數(shù)資料
| 型號： | W6692A |
| 英文描述： | TE Mode S/T Controller with PCI 2.2 Interface and ACPT |
| 中文描述： | TE模S / T的2.2與PCI控制器接口和ACPT |
| 文件頁數(shù)： | 49/101頁 |
| 文件大?。?/td> | 851K |
| 代理商： | W6692A |
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W6692A
Publication Release Date: July 2000
- 49 -
Revision A1
8.1.1 D_ch receive FIFO
D_RFIFO
Read Address 00H/00H
The D_RFIFO has a length of 128 bytes.
After a D_RMR interrupt, exactly 64 bytes are available.
After a D_RME interrupt, the number of bytes available equals RBC5-0 bits in the D_RBCL register.
8.1.2 D_ch transmit FIFO
D_XFIFO
Write Address 04H/01H
The D_XFIFO has a length of 128 bytes.
After an D_XFR interrupt, up to 64 bytes of data can be written into this FIFO for transmission. At the
first time, up to 128 bytes of data can be written.
8.1.3 D_ch command register D_CMDR
Write Address 08H/02H
Value after reset: 00H
7
6
5
4
3
2
1
0
RACK
RRST
0
STT1
XMS
0
XME
XRST
RACK Receive Acknowledge
After a D_RMR or D_RME interrupt, the processor must read out the data in D_RFIFO and then sets
this bit to acknowledge the interrupt. Writing “0” to this bit has no effect.
RRST Receiver Reset
Setting this bit resets the D_ch HDLC receiver and clears the D_RFIFO data. Writing “0” to this bit
has no effect.
STT1 Start Timer 1
The timer 1 is started when this bit is set to one. The timer is stopped when it expires or by a write of
the TIMR1 register. Writing “0” to this bit has no effect.
XMS Transmit Message Start/Continue
Setting this bit will start or continue the transmission of a frame. The opening flag is automatically
added by the HDLC controller. Writing “0” to this bit has no effect.
XME Transmit Message End
Setting this bit indicates the end of frame transmission.. The D_ch HDLC controller automatically
appends the CRC and the closing flag after the data transmission. Writing “0” to this bit has no effect.
Note
: If the frame
≤
64 bytes, XME plus XMS commands must be issued at the same time.
XRST Transmitter Reset
Setting this bit resets the D_ch HDLC transmitter and clears the D_XFIFO. The transmitter will send
inter frame time fill pattern (which is 1's) immediately. This command also results in a transmit FIFO
ready condition. Writing “0” to this bit has no effect.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| W6692ACD | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694A | TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | USB Bus ISDN S/T-Controller |
| W7020 | Telecommunication IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| W6692ACD | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6692ACF | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ISDN LINE INTERFACE|BASIC|CMOS|QFP|100PIN|PLASTIC |
| W6694 | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
| W6694A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:TE Mode S/T Controller with USB 1.1 Interface |
| W6694CD | 制造商:WINBOND 制造商全稱:Winbond 功能描述:USB Bus ISDN S/T-Controller |
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