參數(shù)資料
型號: W6692A
英文描述: TE Mode S/T Controller with PCI 2.2 Interface and ACPT
中文描述: TE模S / T的2.2與PCI控制器接口和ACPT
文件頁數(shù): 55/101頁
文件大?。?/td> 851K
代理商: W6692A
W6692A
Publication Release Date: July 2000
- 55 -
Revision A1
RMB Receive Message Aborted
A "1" means that a sequence of seven 1's was received and the frame is aborted. Software must
issue RRST command to reset the receiver.
Note
: Normally D_RSTA register should be read by the microprocessor after a D_RME interrupt. The contents of D_RSTA are valid
only after a D_RME interrupt and remain valid until the frame is acknowledged via a RACK bit.
8.1.12 D_ch SAPI Address Mask D_SAM Read/Write Address 2CH/0BH
Value after reset: 00H
7
6
5
4
3
2
1
0
SAM7
SAM6
SAM5
SAM4
SAM3
SAM2
SAM1
SAM0
This register masks(disables) the first byte address comparison of the incoming frame. If the mask bit
is "1" the corresponding bit comparisons with D_SAP1, D_SAP2 are disabled. Comparison with
SAPG is always performed.
Note
: For the LAPD frame, the least significant two bits are the C/R bit and EA = 0 bit. It is suggested that the comparison with C/R
bit be masked. EA = 0 for two octet address frame e.g LAPD, EA = 1 for one octet address frame.
8.1.13 D_ch SAPI1 Register
D_SAP1 Read/Write Address 30H/0CH
Value after reset: 00H
7
6
5
4
3
2
1
0
SA17
SA16
SA15
SA14
SA13
SA12
SA11
SA10
This register contains the first choice of the first byte address of received frame. For LAPD frame,
SA17 - SA12 is the SAPI value, SA11 is C/R bit and SA10 is zero.
8.1.14 D_ch SAPI2 Register
D_SAP2
Read/Write Address 34H/0DH
Value after reset: 00H
7
6
5
4
3
2
1
0
SA27
SA26
SA25
SA24
SA23
SA22
SA21
SA20
This register contains the second choice of the first byte address of received frame. For LAPD frame,
SA27 - SA22 is the SAPI value, SA21 is C/R bit and SA20 is zero.
8.1.15 D_ch TEI Address Mask D_TAM Read/Write Address 38H/0EH
Value after reset: 00H
7
6
5
4
3
2
1
0
TAM7
TAM6
TAM5
TAM4
TAM3
TAM2
TAM1
TAM0
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