參數(shù)資料
型號(hào): W6692A
英文描述: TE Mode S/T Controller with PCI 2.2 Interface and ACPT
中文描述: TE模S / T的2.2與PCI控制器接口和ACPT
文件頁(yè)數(shù): 81/101頁(yè)
文件大?。?/td> 851K
代理商: W6692A
W6692A
Publication Release Date: July 2000
- 81 -
Revision A1
8.4.2 Status/Command Register Read/Write
Address 04
H
PCI Configuration Address: 04
H
Default: 0210 0000
H
31
DPE
30
--
29
--
28
--
27
STA
26
DEVSEL
25
24
--
23
FBT
22
UDF
21
66M
20
CAP
19
18
17
16
--
15
14
13
12
11
10
9
--
8
--
7
--
6
5
4
3
2
1
0
--
PEE
--
MAE
IO
AE
Bits 31-16 are Status register and bits 15-0 are Command register. Reads to Status register behave
normally. Bits in Status register are cleared if the corresponding write data bits are '1' in a write
operation.
Bits 15-0 are Command register. When 00
H
is written to this register, the device is logically
disconnected from the PCI bus for all accesses except configuration accesses. The power up value of
Command register is 00
H
Bit 31 DPE Detected Parity Error R/W_clr
1 = A parity error is detected.
0 = No parity error is detected.
Bit 30 SSE Signaled System Error
Not implemented. Read as 0.
Bits 29-28 Master Aborted, Target Aborted
Not implemented. Read as 0.
Bit 27 STA Signaled Target Abort R/W_clr
1 = Target Abort is signaled.
0 = Target Abort is not signaled.
Bits 26-25 DEVSEL Timing Read_only
01 = Medium DEVSEL# timing.
Bits 24 PERR# Asserted
Not implemented. Read as 0.
Bit 23 FBT Fast Back-to-back Transaction Read_only
0 = Unable to accept fast back-to-back transaction.
Bit 22 UDF User Definable Features Read_only
0 = Unable to support User Definable Features.
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