參數(shù)資料
型號: W6692A
英文描述: TE Mode S/T Controller with PCI 2.2 Interface and ACPT
中文描述: TE模S / T的2.2與PCI控制器接口和ACPT
文件頁數(shù): 32/101頁
文件大?。?/td> 851K
代理商: W6692A
W6692A
- 32 -
7.3 Serial Interface Bus
The 192 kbps S/T interface signal consists of two B channels (64 kbps each), one D channel (16
kbps) and other control signals. The multiplexing/demultiplexing functions are carried out in the Serial
Interface Bus (SIB) block. In addition, the B1 and B2 channels can be individually set to carry 64 kbps
or 56 kbps traffic.
7.4 B Channel Switching
There are three switching terminals in W6692A: layer 1, layer 2, CODEC interface. Layer 1 can be
S/T or U. CODEC interface can be PCM port or GCI bus. They are set in in GCR register.
GMODE
GACT
Layer 1
CODEC Interface
GCI Mode
0
0
internal S/T
PCM Port
Master
0
1
internal S/T
GCI Bus
Master
1
x
external
U transceiver
PCM Port
Slave
The B1 and B2 channel switchings are programmed independently. The switching matrix is controlled
by PXC bit in PCTL register and B1_SW[1:0], B2_SW[1:0] bits in B1_MODE and B2_MODE registers
as follows :
PCM1/GCI_B1 Receive Table
PXC
B1_SW[1:0]
B2_SW[1:0]
PCM1/GCI_B1 Rx
0
00
xx
L1_B1
0
01
xx
L1_B1
0
10
xx
L2_B1
0
11
xx
PCM1/GCI_B1
1
xx
00
L1_B2
1
xx
01
L1_B2
1
xx
10
L2_B2
1
xx
11
PCM2/GCI_B2
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