參數(shù)資料
型號: W6692A
英文描述: TE Mode S/T Controller with PCI 2.2 Interface and ACPT
中文描述: TE模S / T的2.2與PCI控制器接口和ACPT
文件頁數(shù): 66/101頁
文件大?。?/td> 851K
代理商: W6692A
W6692A
- 66 -
XD7-0 Peripheral Data
During data phase of peripheral access, they are outputs to XAD7-0 if write, or inputs from XAD7-0 if
read.
8.1.35 Serial EEPROM Control Register EPCTL Read/Write Address FCH/3FH
Value after reset: X0H
7
0
6
0
5
0
4
3
2
1
0
SDI
EN
SK
CS
SDO
SDI Input Data of EPSDI
When read, this bit returns the current data on pin EPSDI. Write operation is ignored.
EN Enable Output
0 : Disable outputs of bits 2-0 to pins.
1 : Enable outputs of bits 2-0 to pins.
SK Output Data of EPSK
When enabled, this bit is output on pin EPSK.
CS Output Data of EPCS
When enabled, this bit is output on pin EPCS.
SDO Output Data of EPSDO
When enabled, this bit is output on pin EPSDO.
A read to bits 3-0 returns the previous written values.
8.1.36 Monitor Receive Channel 1 Register MO1R
Read Address 6DH/40H
Value after reset: FFH
7
6
5
4
3
2
1
0
Contains the Monitor channel data received in GCI Monitor channel 1 according to the Monitor
channel protocol.
8.1.37 Monitor Transmit Channel 1 Register MO1X
Read/Write
Address 71H/41H
Value after reset: FFH
7
6
5
4
3
2
1
0
Contains the Monitor channel data transmitted in GCI Monitor channel 1 according to the Monitor
channel protocol.
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