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| 型號： | WEDPNF8M721V-XBX |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module(8Mx72同步動態(tài)RAM+8M位閃速存儲器混合型模塊) |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊（8Mx72同步動態(tài)RAM的800萬位閃速存儲器混合型模塊） |
| 文件頁數(shù)： | 13/42頁 |
| 文件大?。?/td> | 686K |
| 代理商： | WEDPNF8M721V-XBX |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
Parameter
Symbol
-100
-125
Unit
Min
Max
Min
Max
Access time from CLK (pos. edge)
CL = 3
CL = 2
t
AC
t
AC
t
AH
t
AS
t
CH
t
CL
t
CK
t
CK
t
CKH
t
CKS
t
CMH
t
CMS
t
DH
t
DS
t
HZ
t
HZ
t
LZ
t
OH
t
OH
N
t
RAS
t
RC
t
RCD
t
REF
t
REF
t
RFC
t
RP
t
RRD
t
T
6
6
6
—
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ns
ns
ns
ns
—
ns
ns
Address hold time
Address setup time
CLK high-level width
CLK low-level width
1
2
3
3
8
1
2
3
3
8
Clock cycle time (6)
CL = 3
CL = 2
10
1
2
1
2
1
2
—
1
2
1
2
1
2
CKE hold time
CKE setup time
CS, RAS, CAS, WE, DQM hold time
CS, RAS, CAS, WE, DQM setup time
Data-in hold time
Data-in setup time
Data-out high-impedance time
CL = 3 (7)
CL = 2 (7)
6
7
6
—
Data-out low-impedance time
Data-out hold time (load)
Data-out hold time (no load) (8)
ACTIVE to PRECHARGE command
ACTIVE to ACTIVE command period
ACTIVE to READ or WRITE delay
Refresh period (4,096 rows) – Commercial, Industrial
Refresh period (4,096 rows) – Military
AUTO REFRESH period
PRECHARGE command period
ACTIVE bank A to ACTIVE bank B command
Transition time (9)
WRITE recovery time
1
3
1
3
1.8
50
70
20
1.8
45
68
20
120,000
120,000
64
16
64
—
70
20
15
0.3
—
20
16
0.3
1.2
1.2
(10)
(11)
t
WR
1 CLK + 7ns
15
80
1 CLK + 7ns
15
78
Exit SELF REFRESH to ACTIVE command
NOTES:
1. The minimum specifications are used only to indicate cycle time at which
proper operation over the full temperature range is ensured.
2. An initial pause of 100ms is required after power-up, followed by two
AUTO REFRESH commands, before proper device operation is ensured.
(V
CC
must be powered up simultaneously.) The two AUTO REFRESH
command wake-ups should be repeated any time the t
REF
refresh require-
ment is exceeded.
3. In addition to meeting the transition rate specification, the clock and CKE
must transit between V
IH
and V
IL
(or between V
IL
and V
IH
) in a monotonic
manner.
4. Outputs measured at 1.5V with equivalent load:
Q
t
XSR
SDRAM ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CHARACTERISTICS
(Notes 1, 2, 3, 4, 5)
5. AC timing and I
CC
tests have V
IL
= 0V and V
IH
= 3V, with timing referenced
to 1.5V crossover point.
6. The clock frequency must remain constant (stable clock is defined as a
signal cycling within timing constraints specified for the clock pin)
during access or precharge states (READ, WRITE, including t
WR
, and
PRECHARGE commands). CKE may be used to reduce the data rate.
7. t
HZ
defines the time at which the output achieves the open circuit
condition; it is not a reference to V
OH
or V
OL
. The last valid data element
will meet t
OH
before going High-Z.
8. Guaranteed by design, but not tested.
9. AC characteristics assume t
T
= 1ns.
10. Auto precharge mode only. The precharge timing budget (t
RP
) begins
7.5ns/7ns after the first clock delay, after the last WRITE is executed.
11. Precharge mode only.
50pF
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M722V-1010BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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