- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄361836 > WEDPNF8M721V-XBX 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module(8Mx72同步動態(tài)RAM+8M位閃速存儲器混合型模塊) PDF資料下載
參數(shù)資料
| 型號： | WEDPNF8M721V-XBX |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module(8Mx72同步動態(tài)RAM+8M位閃速存儲器混合型模塊) |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊（8Mx72同步動態(tài)RAM的800萬位閃速存儲器混合型模塊） |
| 文件頁數(shù)： | 18/42頁 |
| 文件大?。?/td> | 686K |
| 代理商： | WEDPNF8M721V-XBX |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁當前第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁
18
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
AUTOSELECT MODE
The autoselect mode provides sector protection verification, through
identifier codes input codes output on FD
7-0
. This mode is prima-
rily intended for programming equipment to automatically match
a device to be programmed with its corresponding programming
algorithm. However, the autoselect codes can also be accessed
in-system through the command register.
When using programming equipment, the autoselect mode re-
quires V
ID
(11.5V to 12.5V) on address pin FA
9
. Address pins FA
6
,
FA
1
, and FA
0
must be as shown in Table 6. In addition, when
verifying sector protection, the sector address must appear on the
appropriate highest order address bits (see Table 5). Table 6
shows the remaining address bits that are “don't care.” When all
necessary bits have been set as required, the programming equip-
ment may then read the corresponding identifier code on FD
7-0
.
To access the autoselect codes in-system, the host system can
issue the autoselect command via the command register, as
shown in Table 7. This method does not require V
ID
. See “Com-
mand Definitions” for details on using the autoselect mode.
SECTOR PROTECTION/UNPROTECTION
The hardware sector protection feature disables both program
and erase operations in any sector. The hardware sector unprotection
feature re-enables both program and erase operations in previ-
ously protected sectors.
The device is shipped with all sectors unprotected.
It is possible to determine whether a sector is protected or
unprotected. See “Autoselect Mode” for details.
This operation requires V
ID
on the RST pin only, and can be
implemented either in-system or via programming equipment.
Figure 5 shows the algorithms and the timing diagram is shown in
figure 18. This method uses standard microprocessor bus cycle
timing. For sector unprotect, all unprotected sectors must first be
protected prior to the first sector unprotect write cycle.
TABLE 6 - AUTOSELECT CODES (HIGH VOLTAGE METHOD)
Description
FCS
FOE
FWE
FA
18
-
12
FA
11
-
10
FA
9
FA
8
-
7
FA
6
FA
5
-
2
FA
1
FA
0
FD
7
-
0
01h
(protected)
00h
(unprotected)
Sector Protection
Verificaton
L
L
H
SA
X
V
ID
X
L
X
H
L
L = Logic Low = V
IL
,
H = Logic High = V
IH
,
SA = Sector Address, X = Don't Care
TEMPORARY SECTOR UNPROTECT
This feature allows temporary unprotection of previously pro-
tected sector groups to change data-in system. The Sector Unprotect
mode is activated by setting the RST pin to V
ID
. During this mode,
formerly protected sector can be programmed or erased by select-
ing the sector addresses. Once V
ID
is removed from the RST pin,
all the previously protected sector groups will be protected again.
Figure 16 shows the algorithm and the timing diagram is shown in
Figure 17, for this feature.
HARDWARE DATA PROTECTION
The command sequence requirement of unlock cycles for pro-
gramming or erasing provides data protection against inadvertent
writes (refer to Table 7 for command definitions). In addition, the
following hardware data protection measures prevent accidental
erasure or programming, which might otherwise be caused by
spurious system level signals during Vcc power-up and power-
down transitions, or from system noise.
Low Vcc Write Inhibit
When Vcc is less than V
LKO
, the device does not accept any write
cycles. This protects data during Vcc power-up and power-down.
The command register and all internal program/erase circuits are
disabled, and the device resets. Subsequent writes are ignored
until Vcc is greater than V
LKO
. The system must provide the proper
signals to the control pins to prevent unintentional writes when
Vcc is greater than V
LKO
.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on FOE, FCS or FWE do not
initiate a write cycle.
Logical Inhibit
Write cycles are inhibited by holding any one of FOE = V
IL
, FCS =
V
IH
or FWE = V
IH
. To initiate a write cycle, FCS and FWE must be
a logical zero while FOE is a logical one.
Power-Up Write Inhibit
If FWE = FCS = V
IL
and FOE = V
IH
during power up, the device does
not accept commands on the rising edge of FWE. The internal
state machine is automatically reset to reading array data on
power-up.
相關PDF資料 |
PDF描述 |
|---|---|
| WEDPNF8M722V-XBX | 8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module(8Mx72同步動態(tài)RAM+16M位閃速存儲器混合型模塊) |
| WEDPS512K32V-XBX | SRAM MCP |
| WEDPS512K32-XBX | SRAM MCP |
| WEDPY256K72V-XBX | SSRAM MCP |
| WEDPZ512K72S-XBX | NBL SSRAM MCP |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| WEDPNF8M722V-1010BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
發(fā)布緊急采購，3分鐘左右您將得到回復。