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| 型號： | WEDPNF8M721V-XBX |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module(8Mx72同步動態(tài)RAM+8M位閃速存儲器混合型模塊) |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊（8Mx72同步動態(tài)RAM的800萬位閃速存儲器混合型模塊） |
| 文件頁數(shù)： | 26/42頁 |
| 文件大?。?/td> | 686K |
| 代理商： | WEDPNF8M721V-XBX |
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26
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
RY/BY1: Ready/Busy
The RY/BY1 is a dedicated, open drain output pin that indicates
whether an Embedded Algorithm is in progress or complete. The
RY/BY1 status is valid after the rising edge of the final FWE pulse
in the command sequence. Since RY/BY1 is an open-drain output,
several RY/BY1 pins can be tied together in parrallel with a pull-
up resistor to Vcc.
If the output is low (Busy), the device is actively erasing or
programming. (This includes programming in the Erase Suspend
mode.) If the output is high (Ready), the device is ready to read
array data (including during the Erase Suspend mode.), or is in the
standby mode.
Table 8 shows the outputs for RY/BY1. Figures
11, 12, 13, 19
show
RY/BY1 for read, program, erase and reset operations, respectively.
FD6: Toggle Bit I
“Toggle Bit I” on FD
6
indicates whether an Embedded Program or
Erase Algorithm is in progress or has been completed, or whether
the device has entered the Erase Suspend mode. Toggle Bit I may
read at any address, and is valid after the rising edge of the final
FWE pulse in the command sequence (prior to the program or
erase operation), and during the sector erase time-out.
During an Embedded Program or Erase Algorithm operation, suc-
cessive read cycles to any address will result in FD
6
toggling. (The
system may use either FOE or FCS to control the read cycles.)
When operation is complete, FD
6
stops toggling.
After the erase command sequence is written, if all selectors
selected for erasing are protected. FD
6
toggles for approximately
100
μ
s, then returns to reading array data. If not all selected
sectors are protected, the Embedded Erase Algorithm erases the
unprotected sectors, and ignores the selected sectors that are
protected.
The system can use FD
6
and FD
2
together to determine whether a
sector is actively erasing or is erase-suspended. When the device
is actively erasing (that is, the Embedded Erase Algorithm is in
progress) FD
6
toggles. When the device enters the Erase Suspend
mode, FD
6
stops toggling. However, the system must also use FD
2
to determine which sectors are erasing or erase-suspended.
Alternatively, the system can use FD
7
(see the subsection on “FD
7
:
Data Polling”).
If a program address falls within a protected sector, FD
6
also
toggles for approximately 1
μ
s after the program command se-
quence is written, then returns to reading array data.
FD
6
also toggles during erase-suspend-program mode, and stops
toggling once the Embedded Program algorithm is complete.
Table 8 shows the outputs for “Toggle Bit I” on FD
6
. Figure 9
shows the Toggle Bit Algorithm. Figure 21 shows the toggle bit
timing diagrams. Figure 20 shows the difference between FD
2
and
FD
6
in graphical form. See also the subsection on “FD
2
: Toggle Bit II”.
FD
2
: Toggle Bit II
The “Toggle Bit II” on FD
2
, when used with FD
6
, indicates whether
a particular sector is actively erasing (that is, the Embedded Erase
Algorithm is in progress) or whether that sector is erase-sus-
pended. “Toggle Bit II” is valid after the rising edge of the final
FWE pulse in the command sequence.
FD
2
toggles when the system reads at addresses within those
sectors that have been selected for erasure. (The system may use
either FOE or FCS to control the read cycles.) FD
2
cannot distin-
guish whether the sector is actively erasing or is erase-sus-
pended. FD
6
, by comparison, indicates whether the device is
actively erasing, or is in Erase Suspend, but cannot distinguish
which sectors are selected for erasure. Thus, both status bits are
required for sector and mode information. Refer to Table 8 to
compare outputs for FD
2
and FD
6
.
Figure 9 shows the Toggle Bit Algorithm in flowchart form, and the
section “FD
2
: Toggle Bit II” explains the algorithm. See also the
subsection on “FD
6
: Toggle Bit I”. Figure 21 shows the toggle bit
timing diagrams. Figure 20 shows the difference between FD
2
and
FD
6
in graphical form.
Reading Toggle Bits FD
6
/FD
2
Refer to Figure 9 for the following discussion. Whenever the
system initially begins reading toggle bit status, it must read FD
7-
FD
0
at least twice in a row to determine whether a toggle bit is
toggling. Typically, the system would note and store the value of
the toggle bit after the first read. After the second read, the
system would compare the new value of the toggle bit with the
first. If the toggle bit is not toggling, the device has completed the
program or erase operation. The system can read array data on
FD
7-0
on the following read cycle.
However, if after the initial two read cycles, the system deter-
mines that the toggle bit is still toggling, the system also should
note whether the value of FD
5
is high (see the section on FD
5
). If
it is, the system should then determine again whether the toggle
bit is toggling, since the toggle bit may have stopped toggling just
as the device has successfully completed the program or erase
operation. If it is still toggling, the device did not complete the
operation successfully, and the system must write the reset
command to return to reading array data.
The remaining scenario is that the system initially determines that
the toggle bit is toggling and FD
5
has not gone high. The system
may continue to monitor the toggle bit and FD
5
through successive
read cycles, determining the status as described in the previous
paragraph. Alternatively, it may choose to perform other system
tasks. In this case, the system must start at the beginning of the
algorithm when it returns to determine the status of the operation
(top of Figure 9).
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| WEDPNF8M722V-1010BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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