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| 型號： | WEDPNF8M721V-XBX |
| 英文描述： | 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module(8Mx72同步動態(tài)RAM+8M位閃速存儲器混合型模塊) |
| 中文描述： | 8Mx72同步DRAM 8MB閃存的混合模塊（8Mx72同步動態(tài)RAM的800萬位閃速存儲器混合型模塊） |
| 文件頁數(shù)： | 7/42頁 |
| 文件大?。?/td> | 686K |
| 代理商： | WEDPNF8M721V-XBX |
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White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
SDRAM DESCRIPTION
The 64MByte (512Mb) SDRAM is a high-speed CMOS, dynamic
random-access ,memory using 5 chips containing 134, 217, 728
bits. Each chip is internally configured as a quad-bank DRAM with
a synchronous interface. Each of the chip’s 33,554,432-bit banks
is organized as 4,096 rows by 512 columns by 16 bits.
Read and write accesses to the SDRAM are burst oriented; ac-
cesses start at a selected location and continue for a programmed
number of locations in a programmed sequence. Accesses begin
with the registration of an ACTIVE command, which is then
followed by a READ or WRITE command. The address bits regis-
tered coincident with the ACTIVE command are used to select the
bank and row to be accessed (BA
0
, BA
1
select the bank; A
0-11
select the row). The address bits registered coincident with the
READ or WRITE command are used to select the starting column
location for the burst access.
The SDRAM provides for programmable READ or WRITE burst
lengths of 1, 2, 4 or 8 locations, or the full page, with a burst
terminate option. An AUTO PRECHARGE function may be enabled
to provide a self-timed row precharge that is initiated at the end
of the burst sequence.
The 64MB SDRAM uses an internal pipelined architecture to
achieve high-speed operation. This architecture is compatible
with the 2n rule of prefetch architectures, but it also allows the
column address to be changed on every clock cycle to achieve a
high-speed, fully random access. Precharging one bank while
accessing one of the other three banks will hide the precharge
cycles and provide seamless, high-speed, random-access operation.
The 64MB SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along with a
power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance, including
the ability to synchronously burst data at a high data rate with
automatic column-address generation, the ability to interleave
between internal banks in order to hide precharge time and the
capability to randomly change column addresses on each clock
cycle during a burst access.
SDRAM FUNCTIONAL DESCRIPTION
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for a pro-
I
CC
SPECIFICATIONS AND CONDITIONS
(Notes 1,2,3,4)
(V
CC
= +3.3V
±
0.3V; T
A
= -55
°
C to +125
°
C)
Parameter/Condition
SDRAM Operating Current: Active Mode;
Burst = 2; Read or Write; t
RC
= t
RC
(min); CAS latency = 3 (5, 6, 7); FCS = High
SDRAM Standby Current: Active Mode; CKE = HIGH; CS = HIGH; FCS = High;
All banks active after t
RCD
met; No accesses in progress (5, 7, 8)
SDRAM Operating Current: Burst Mode; Continuous burst; FCS = High
Read or Write; All banks active; CAS latency = 3 (5, 6, 7)
SDRAM Self Refresh Current; FCS = High (14)
Symbol
Max
Units
I
CC1
750
mA
I
CC3
250
mA
I
CC4
750
mA
I
CC7
10
mA
Flash V
CC
Active Current for Read : FCS = V
IL
, FOE = V
IH
, f = 5MHz (9, 13); CS = CKE = High
I
FCC1
40
mA
Flash V
CC
Active Current for Program or Erase: FCS = V
IL
, FOE = V
IH
(10, 13); CS = CKE = High
I
FCC2
45
mA
Flash V
CC
Standby Current: V
CC
= 3.6, FCS = V
IH
, f = 5MHz; CS = CKE = High (13)
I
FCC3
10
mA
NOTES:
1. All voltages referenced to V
SS
.
2. An initial pause of 100ms is required after power-up, followed by two
AUTO REFRESH commands, before proper device operation is ensured.
(V
CC
must be powered up simultaneously.) The two AUTO REFRESH
command wake-ups should be repeated any time the t
REF
refresh requirement
is exceeded.
3. AC timing and I
CC
tests have V
IL
= 0V and V
IH
= 3V, with timing referenced
to 1.5V crossover point.
4. I
CC
specifications are tested after the device is properly initialized.
5. I
CC
is dependent on output loading and cycle rates. Specified values are
obtained with minimum cycle time and the outputs open.
6. The I
CC
current will decrease as the CAS latency is reduced. This is due to
the fact that the maximum cycle rate is slower as the CAS latency is
reduced.
7. Address transitions average one transition every two clocks.
8. Other input signals are allowed to transition no more than once every two
clocks and are otherwise at valid
V
IH
or V
IL
levels.
9. The I
CC
current listed includes both the DC operating current and the
frequency dependent component (at 5 MHz). The frequency component
typically is less than 8 mA/MHz, with OE at V
IH
.
10. I
CC
active while Embedded Algorithm (program or erase) is in progress.
11. Maximum I
CC
specifications are tested with V
CC
= V
CC
Max.
12. Automatic sleep mode enables the low power mode when addressed
remain stable for tacc + 30 ns.
13. SDRAM in self refresh mode
14. Self refresh available in commercial and industrial temperatures only.
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| WEDPNF8M722V-1010BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1010BM | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BC | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
| WEDPNF8M722V-1012BI | 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package |
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