參數(shù)資料
型號(hào)： WEDPNF8M721V-XBX
英文描述： 8Mx72 Synchronous DRAM + 8Mb Flash Mixed Module(8Mx72同步動(dòng)態(tài)RAM+8M位閃速存儲(chǔ)器混合型模塊)
中文描述： 8Mx72同步DRAM 8MB閃存的混合模塊（8Mx72同步動(dòng)態(tài)RAM的800萬(wàn)位閃速存儲(chǔ)器混合型模塊）
文件頁(yè)數(shù)： 16/42頁(yè)
文件大?。?/td> 686K
代理商： WEDPNF8M721V-XBX
16
White Electronic Designs Corporation (602) 437-1520 www.whiteedc.com
WEDPNF8M721V-XBX
REQUIREMENTS FOR READING ARRAY DATA
To read array data from the outputs, the system must drive the FCS
and FOE pins to V
IL
. FCS is the power control and selects the
device. FOE is the output control and gates array data to the output
pins. FWE should remain at V
IH
. The BYTE1 pin determines whether
the device outputs array data in words or bytes.
The internal state machine is set for reading array data upon
device power-up, or after a hardware reset. This ensures that no
spurious alteration of the memory content occurs during the
power transition. No command is necessary in this mode to obtain
array data. Standard microprocessor read cycles that assert valid
addresses on the device data outputs. The device remains en-
abled for read access until the command register contents are
altered.
See “Reading Array Data” for more information. Refer to the Flash
AC Read-only Operations table for timing specifications and to
Figure 11 for the timing diagram. I
FCC1
in the I
CC
Specifications and
Conditions table represents the active current specification for
reading array data.
WRITE COMMANDS/COMMAND SEQUENCES
To writes a command or command sequence (which includes
programming data to the device and erasing sectors of memory),
the system must drive FWE and FCS to V
IL
, and FOE to V
IH
.
For program operations, the BYTE1 pin determines whether the
device accepts program data in bytes or words. Refer to “Word/
Byte Configuration” for more information.
The device features an Unlock Bypass mode to facilitate faster
programming. Once the device enters the Unlock Bypass mode,
only two write cycles are required to program a byte, instead of four.
An erase operation can erase one sector, multiple sectors, or the
entire device. Table 5 indicates the address space that each
sector occupies. A “sector address” consists of the address bits
required to uniquely select a sector. The “Flash Command Defini-
tions” section has details on erasing a sector or the entire chip, or
suspending/resuming the erase operation.
After the system writes the autoselect command sequence, the
device enters the autoselect mode. The system can then read
autoselect codes from the internal register (which is separate
from the memory array) on FD
7-0
. Standard read cycle timings
apply in this mode. Refer to the "Autoselect Mode" and "Autoselect
Command Sequence" sections for more information.
I
FCC2
in the DC Characteristics table represents the active current
specifications for the write mode. The “Flash AC Characteristics”
section contains timing specification tables and timing diagrams
for write operations.
PROGRAM AND ERASE OPERATION STATUS
During an erase or program operation, the system may check the
status of the operation by reading the status bits on FD
7-0
.
Standard read cycle timings and I
FCC
read specifications apply.
Refer to “Write Operation Status” for more information, and to
“Flash AC Characteristics” for timing diagrams.
TABLE 4 - DEVICE BUS OPERATIONS
LEGEND:
L
= Logic Low = V
IL
H
= Logic High = V
IH
V
ID
= 12.0
±
0.5V
NOTES:
1. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the "Sector Protection/Unprotection" section.
2. Addresses are FA18: FA0 in word mode (BYTE1 = V
IH
), FA18: FA-1 in byte mode (BYTE1 = V
IL
)
X
FA
IN
FD
IN
= Don’t Care
= Flash Address In
= Flash Data In
FD
OUT
= Flash Data Out
FD
8-15
Operation
FCS
FOE
FWE
RST
Addresses (2)
FD
0-7
BYTE1
= V
IH
FD
OUT
FD
OUT
High Z
High Z
High Z
BYTE1
=V
IL
Read
Write
Standby
Output Disable
Reset
L
L
L
H
X
H
X
H
L
X
H
X
H
H
FA
IN
FA
IN
X
X
X
FD
OUT
FD
OUT
High Z
High Z
High Z
FD
8-14
= High Z
FD
15
= FA-
1
High Z
High Z
High Z
Vcc
±
0.3V
L
X
Vcc
±
0.3V
H
L
Sector Address,
FA
6
= L, FA
1
= H,
FA
0
= L
Sector Address,
FA
6
= H, FA
1
= H,
FA
0
= L
A
IN
Sector Protect (1)
L
H
L
V
ID
FD
IN
X
X
Sector Unprotect (1)
L
H
L
V
ID
FD
IN
X
X
Temporary Sector Unprotect
X
X
X
V
ID
FD
IN
FD
IN
High Z
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WEDPNF8M722V-1010BI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1010BM 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1012BC 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
WEDPNF8M722V-1012BI 制造商:WEDC 制造商全稱:White Electronic Designs Corporation 功能描述:8Mx72 Synchronous DRAM + 16Mb Flash Mixed Module Multi-Chip Package
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