參數(shù)資料
型號： XC2S200E-6FGG456C
廠商： Xilinx Inc
文件頁數(shù)： 23/108頁
文件大小： 0K
描述： IC SPARTAN-IIE FPGA 200K 456FBGA
標(biāo)準(zhǔn)包裝： 60
系列： Spartan®-IIE
LAB/CLB數(shù)： 1176
邏輯元件/單元數(shù)： 5292
RAM 位總計： 57344
輸入/輸出數(shù)： 289
門數(shù)： 200000
電源電壓： 1.71 V ~ 1.89 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 85°C
封裝/外殼： 456-BBGA
供應(yīng)商設(shè)備封裝： 456-FBGA
其它名稱： 122-1323
DS077-2 (v3.0) August 9, 2013
21
Product Specification
Spartan-IIE FPGA Family: Functional Description
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
design, thus allowing the most convenient entry method to
be used for each portion of the design.
Design Implementation
The place-and-route tools automatically provide the imple-
mentation flow described in this section. The partitioner
takes the EDIF netlist for the design and maps the logic into
the architectural resources of the FPGA (CLBs and IOBs,
for example). The placer then determines the best locations
for these blocks based on their interconnections and the
desired performance. Finally, the router interconnects the
blocks.
The algorithms support fully automatic implementation of
most designs. For demanding applications, however, the
user can exercise various degrees of control over the pro-
cess. User partitioning, placement, and routing information
is optionally specified during the design-entry process. The
implementation of highly structured designs can benefit
greatly from basic floorplanning.
The implementation software incorporates timing-driven
placement and routing. Designers specify timing require-
ments along entire paths during design entry. The timing
path analysis routines then recognize these user-specified
requirements and accommodate them.
Timing requirements are entered in a form directly relating
to the system requirements, such as the targeted clock fre-
quency, or the maximum allowable delay between two reg-
isters. In this way, the overall performance of the system
along entire signal paths is automatically tailored to
user-generated specifications. Specific timing information
for individual nets is unnecessary.
Design Verification
In addition to conventional software simulation, FPGA users
can use in-circuit debugging techniques. Because Xilinx
devices are infinitely reprogrammable, designs can be veri-
fied in real time without the need for extensive sets of soft-
ware simulation vectors.
The development system supports both software simulation
and in-circuit debugging techniques. For simulation, the
system extracts the post-layout timing information from the
design database, and back-annotates this information into
the netlist for use by the simulator. Alternatively, the user
can verify timing-critical portions of the design using the
static timing analyzer.
For in-circuit debugging, Xilinx offers a download cable,
which connects the FPGA in the target system to a PC or
workstation. After downloading the design into the FPGA,
the designer can read back the contents of the flip-flops,
and so observe the internal logic state. Simple modifica-
tions can be downloaded into the system in a matter of min-
utes.
Configuration
Configuration is the process by which the bitstream of a
design, as generated by the Xilinx development software, is
loaded into the internal configuration memory of the FPGA.
Spartan-IIE devices support both serial configuration, using
the master/slave serial and JTAG modes, as well as
byte-wide configuration employing the Slave Parallel mode.
Configuration File
Spartan-IIE devices are configured by sequentially loading
frames of data that have been concatenated into a configu-
ration file. Table 10 shows how much nonvolatile storage
space is needed for Spartan-IIE devices.
It is important to note that, while a PROM is commonly used
to store configuration data before loading them into the
FPGA, it is by no means required. Any of a number of differ-
ent kinds of under populated nonvolatile storage already
available either on or off the board (for example, hard drives,
FLASH cards, and so on) can be used.
Modes
Spartan-IIE devices support the following four configuration
modes:
Slave Serial mode
Master Serial mode
Slave Parallel mode
Boundary-scan mode
The Configuration mode pins (M2, M1, M0) select among
these configuration modes with the option in each case of
having the IOB pins either pulled up or left floating prior to
the end of configuration. The selection codes are listed in
Configuration through the boundary-scan port is always
available, independent of the mode selection. Selecting the
boundary-scan mode simply turns off the other modes. The
three mode pins have internal pull-up resistors, and default
to a logic High if left unconnected.
Table 10: Spartan-IIE Configuration File Size
Device
Configuration File Size (Bits)
XC2S50E
630,048
XC2S100E
863,840
XC2S150E
1,134,496
XC2S200E
1,442,016
XC2S300E
1,875,648
XC2S400E
2,693,440
XC2S600E
3,961,632
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