參數(shù)資料
型號(hào): XC2S200E-6FGG456C
廠商: Xilinx Inc
文件頁數(shù): 68/108頁
文件大?。?/td> 0K
描述: IC SPARTAN-IIE FPGA 200K 456FBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 1176
邏輯元件/單元數(shù): 5292
RAM 位總計(jì): 57344
輸入/輸出數(shù): 289
門數(shù): 200000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
其它名稱: 122-1323
62
DS077-4 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: Pinout Tables
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
I/O, VREF
Bank 6,
L39P
6
P45
XC2S100E,
150E
All
I/O, L39N
6
P46
XC2S100E,
150E
-
I/O
6
P47
-
XC2S200E,
300E
I/O,
L38P_YY
6
P48
All
-
I/O,
L38N_YY
6
P49
All
-
M1
-
P50
-
GND
-
P51
-
M0
-
P52
-
VCCO
-
P53
-
M2
-
P54
-
I/O,
L37N_YY
5
P55
All
-
I/O,
L37P_YY
5
P56
All
-
I/O
5
P57
-
XC2S200E,
300E
I/O
5
P58
-
I/O, VREF
Bank 5,
L36N_YY
5
P59
All
I/O,
L36P_YY
5
P60
All
-
I/O, L35N
5
P61
XC2S50E,
100E, 300E
-
I/O, L35P
5
P62
XC2S50E,
100E, 300E
-
I/O, L34N
5
P63
XC2S50E,
100E, 200E,
300E
XC2S100E,
150E, 200E,
300E
I/O, L34P
5
P64
XC2S50E,
100E, 200E,
300E
-
GND
-
P65
-
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
VCCO
-
P66
-
VCCINT
-
P67
-
I/O, L33N
5
P68
XC2S50E,
100E, 200E,
300E
-
I/O, L33P
5
P69
XC2S50E,
100E, 200E,
300E
-
I/O
5
P70
-
I/O, L32N
5
P71
XC2S100E,
150E
-
GND
-
P72
-
I/O, VREF
Bank 5,
L32P
5
P73
XC2S100E,
150E
All
I/O
5
P74
-
I/O (DLL),
L31N
5
P75
-
VCCINT
-
P76
-
GCK1, I
5
P77
-
VCCO
-
P78
-
GND
-
P79
-
GCK0, I
4
P80
-
I/O (DLL),
L31P
4
P81
-
I/O
4
P82
-
I/O, L30N
4
P83
XC2S50E,
200E, 300E
-
I/O, VREF
Bank 4,
L30P
4
P84
XC2S50E,
200E, 300E
All
GND
-
P85
-
I/O, L29N
4
P86
XC2S50E,
200E, 300E
-
I/O, L29P
4
P87
XC2S50E,
200E, 300E
-
I/O, L28N
4
P88
XC2S50E,
100E, 200E,
300E
-
PQ208 Pinouts (XC2S50E, XC2S100E,
XC2S150E, XC2S200E, XC2S300E)
Pad Name
Pin
LVDS
Async.
Output
Option
VREF
Option
Function
Bank
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