參數(shù)資料
型號: XC2S200E-6FGG456C
廠商: Xilinx Inc
文件頁數(shù): 52/108頁
文件大小: 0K
描述: IC SPARTAN-IIE FPGA 200K 456FBGA
標(biāo)準(zhǔn)包裝: 60
系列: Spartan®-IIE
LAB/CLB數(shù): 1176
邏輯元件/單元數(shù): 5292
RAM 位總計(jì): 57344
輸入/輸出數(shù): 289
門數(shù): 200000
電源電壓: 1.71 V ~ 1.89 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 85°C
封裝/外殼: 456-BBGA
供應(yīng)商設(shè)備封裝: 456-FBGA
其它名稱: 122-1323
48
DS077-3 (v3.0) August 9, 2013
Product Specification
Spartan-IIE FPGA Family: DC and Switching Characteristics
R
— OBSOLETE — OBSOLETE — OBSOLETE — OBSOLETE —
TBUF Switching Characteristics
JTAG Test Access Port Switching Characteristics
Configuration Switching Characteristics
Symbol
Description
Speed Grade
Units
-7
-6
Max
TIO
IN input to OUT output
0
ns
TOFF
TRI input to OUT output high impedance
0.1
0.11
ns
TON
TRI input to valid data on OUT output
0.1
0.11
ns
Symbol
Description
Speed Grade
Units
-7
-6
Min
Max
Min
Max
Setup/Hold Times with Respect to TCK
TTAPTCK / TTCKTAP
TMS and TDI setup times and hold times
4.0 / 2.0
-
4.0 / 2.0
-
ns
Sequential Delays
TTCKTDO
Output delay from clock TCK to output TDO
-
11.0
-
11.0
ns
FTCK
TCK clock frequency
-
33
-
33
MHz
Notes:
1.
Before configuration can begin, VCCINT and VCCO Bank 2 must reach the recommended operating voltage.
Figure 23: Configuration Timing on Power-Up
DS001_12_102301
TPOR
TPL
TICCK
Valid
CCLK Output or Input
M0, M1, M2
(Required)
PROGRAM
INIT
VCC(1)
.
Symbol
Description
All Devices
Units
Min
Max
TPOR
Power-on reset
-
2
ms
TPL
Program latency
-
100
μs
TICCK
CCLK output delay (Master serial
mode only)
0.5
4
μs
TPROGRAM
Program pulse width
300
-
ns
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