參數(shù)資料
型號(hào)： XR88C681CJ-F
廠商： Exar Corporation
文件頁(yè)數(shù)： 24/101頁(yè)
文件大小： 0K
描述： IC UART CMOS DUAL 44PLCC
標(biāo)準(zhǔn)包裝： 27
特點(diǎn)： *
通道數(shù)： 2，DUART
FIFO's： 1 字節(jié)，3 字節(jié)
電源電壓： 4.75 V ~ 5.25 V
帶并行端口： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 44-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 44-PLCC（16.59x16.59）
包裝： 管件
其它名稱： 1016-1327-5
XR88C681
29
Rev. 2.11
vectored-interrupt processing. Hence, when -INTA is
asserted, the CPU module is awaiting “vector”
information on the Data bus. In the case of the 8080A
CPU Module, this “vector” information is typically the
op-code for one of the RESTART instructions (RST). The
8080A CPU supports up to eight different RST
instructions (RST 0 through RST 7). These instructions
are one-byte calls to specific locations within the CPU’s
memory space, where the appropriate interrupt service
routine exists.
Table 10 presents a list of these RESTART
instructions, the op-codes, and the corresponding
RESTART address.
Op-Code (hex)
Mnemonic
Restart Address
(hex)
C7
RST 0
0000
CF
RST 1
0008
D7
RST 2
0010
DF
RST 3
0018
E7
RST 4
0020
EF
RST 5
0028
F7
RST 6
0030
FF
RST 7
0038
Table 10. 8080A and 8085 CPU Restart Instructions
Used With Vectored Interrupts
Therefore, once the CPU receives the op-code for one of
these RESTART instructions, it will begin executing this
instruction by loading the Program Counter will the
appropriate “Restart Address”. Afterwards, program
control will be branched to the “Restart Address” location.
For Example:
If the op-code “E716” is loaded onto the Data Bus during
the -INTA cycle, this op-code corresponds with the “RST
4” command and, the CPU will load 002016 into the
Program Counter and program control will branch to that
location in memory (see
Table 10).
Interfacing the 8080 CPU Module to the XR88C681
DUART for Interrupt Processing
The 8080A CPU can be connected to the XR88C681 and
run in the Interrupt Driven mode.
Figure 7 presents an
approach that can be applied to interfacing the
XR88C681 DUART to the 8080A CPU for “external”
vectored interrupt processing.
Please note that Figure 8
only includes information pertaining to DUART interrupt
servicing. Other circuitry (such as the 8224 Clock
Generator, the Address Bus, etc.) have been omitted from
the schematic. In this schematic, the DUART Interrupt
Service Routine is located at 002016 in memory.
Additionally, the DUART has been configured to operate
in the I-Mode. The function description of this circuit is
presented here.
The XR88C681 will request an interrupt to the 8080A
CPU, by toggling its -INTR output “l(fā)ow”. This signal is
inverted and applied to the active-high INT input of the
CPU. Once the 8080A CPU has completed its current
instruction, it will assert the active-low -INTA signal (from
the 8228 Bi-Directional Bus Driver). At this time, both the
-INTR signal (from the DUART) and the -INTA signal
(from the 8228) are each at a logic “l(fā)ow”. The -INTR and
-INTA signals are both routed to a two-input OR gate.
Hence, when both -INTR and -INTA are at logic “l(fā)ow”, the
output of the OR-gate will also be at a logic “l(fā)ow”, and
thereby asserting both of the Output Enable (OE) inputs
of the SN74LS244 Data Bus buffer (U3). This “ORing” of
the -INTR and -INTA signals is used to insure that only the
peripheral device requesting the interrupt is the one that
receives the service (e.g., responsive to the asserted
-INTA signal). Once both -OE inputs of U3 are asserted,
the data, applied at the input of this device (U3) will now
appear at the output of this device, and at the D7 - D0
inputs of the 8228 device (U2).
Please note that, in this
example, the value “E716” is hard-wired into the input of
U3. This value is the op-code for the “RST 4” command.
Hence, once this data is gated into the CPU module, via
the data bus, the CPU will load 002016 into its Program
Counter and branch program control to that location. The
Interrupt Service Routine for the DUART exists at this
location in memory.
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