參數(shù)資料
型號(hào): XR88C681CJ-F
廠商: Exar Corporation
文件頁(yè)數(shù): 47/101頁(yè)
文件大?。?/td> 0K
描述: IC UART CMOS DUAL 44PLCC
標(biāo)準(zhǔn)包裝: 27
特點(diǎn): *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應(yīng)商設(shè)備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱(chēng): 1016-1327-5
XR88C681
5
Rev. 2.11
44 PLCC
40 PDIP,
CDIP
28 PDIP
Symbol
Type
Description
14
12
9
OP1
(-RTSB)
O
Output 1 (General Purpose Output).
This output can also
be programmed to function as the active-low, “Channel B
Request-to-Send” Output (-RTSB).
15
13
OP3
(TXCB_1X)
(RXCB_1X)
(-C/T_RDY)
O
Output 3 (General Purpose Output).
This output port can
also be programmed to function as: the “Channel B Trans-
mitter 1X clock” output (TXCB_1X), the “Channel B Receiv-
er 1X clock” output (RXCB_1X), or the open drain, active-
low “Counter/Timer Ready” output (-C/T_RDY).
16
14
OP5
(-RXRDY/
-FFULL_B)
O
Output 5 (General Purpose Output Pin).
This output port
pin can also be programmed to function as the open-drain,
active-low, Channel B “Receive Ready” or “Receiver FIFO
Full” indicator output (-RXRDY_B/-FFULL_B).
17
15
OP7
(TXRDY_B)
O
Output 7. (General Purpose Output Pin).
This output port
pin can also be programmed to function as the open-drain,
active-low, “Transmitter Ready” indicator output for Channel
B (-TXRDY_B).
18
16
10
D1
I/O
Bi-Directional Data Bus.
19
17
11
D3
I/O
Bi-Directional Data Bus.
20
18
12
D5
I/O
Bi-Directional Data Bus.
21
19
13
D7
I/O
MSB of the Eight Bit Bi-Directional Data Bus.
All transfers
between the CPU and the DUART take place over this bus
(consisting of pins D0 - D7). The bus is tri-stated when the
-
CS input is “high”, except during an IACK cycle (in the Z-
Mode).
22
20
14
GND
PWR
Signal Ground.
23
NC
No Connect.
24
21
15
-
INTR
O
Interrupt Request Output (Active Low, Open Drain).
-
INTR is asserted upon the occurrence of one or more of the
chip’s maskable interrupting conditions. This signal will re-
main asserted throughout the Interrupt Service Routine and
will be negated once the condition(s) causing the Interrupt
Request has been eliminated.
25
22
16
D6
I/O
Bi-Directional Data Bus.
26
23
17
D4
I/O
Bi-Directional Data Bus.
27
24
18
D2
I/O
Bi-Directional Data Bus.
28
25
19
D0
I/O
LSB of the Eight Bit Bi-Directional Data Bus.
All transfers
between the CPU and the DUART take place over this bus.
The bus is tri-stated when the -CS input is “high”, except
during an IACK cycle (in the Z-Mode).
29
26
OP6
(-TXRDY_A)
O
Output 6 (General Purpose Output).
This output pin can
also be programmed to function as the open drain, active-
low, “Transmitter Ready” indicator output for Channel A
(-TXRDY_A).
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