參數(shù)資料
型號: XR88C681CJ-F
廠商: Exar Corporation
文件頁數(shù): 39/101頁
文件大?。?/td> 0K
描述: IC UART CMOS DUAL 44PLCC
標準包裝: 27
特點: *
通道數(shù): 2,DUART
FIFO's: 1 字節(jié),3 字節(jié)
電源電壓: 4.75 V ~ 5.25 V
帶并行端口:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 44-LCC(J 形引線)
供應商設備封裝: 44-PLCC(16.59x16.59)
包裝: 管件
其它名稱: 1016-1327-5
XR88C681
42
Rev. 2.11
Z-80 P can be configured to operate in one of three
different “interrupt modes”. The Z-80 is also a little bit less
complicated to interface to (than some of the P/ Cs
previously mentioned) because its address and data bus
are not multiplexed.
Figure 17 presents a schematic of
the pin out of the Z-80 P.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
A11
A12
A13
A14
A15
PHI
D4
D3
D5
D6
VCC
D2
D7
D0
D1
-INT
-NMI
-HALT
-MREQ
-IORQ
-RD
-WR
-BUSAK
-WAIT
-BUSRQ
-RESET
-M1
-RFSH
GND
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Z80 CPU
Figure 17. Pin Out of the Z80 CPU Device
The Z-80 CPU will support Read/Write operations
between memory and I/O. The Z-80 does require some
additional glue logic in order to interface directly to
memory and peripheral devices. For instance, the Z-80
CPU device does not come with the control bus signals:
-
MEMR (Memory Read), -MEMW (Memory Write), -IOR
(I/O Port Read), -IOW (I/O Port Write) or -IACK/-INTA
(Interrupt Acknowledge) pins. Each of these functions
can be derived from the -RD, -WR, -IORQ, -MREQ and
-
M1 pins.
Figure 18 presents a schematic of the Z-80
CPU Module, which shows how once can extract the
control bus signals from these CPU control pins.
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