參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 11/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標準包裝: 1
系列: Hercules™ ARM® RM4x
應用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應商設備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.19 Reset / Abort / Error Sources
Table 4-36. Reset/Abort/Error Sources
ESM HOOKUP
ERROR SOURCE
SYSTEM MODE
ERROR RESPONSE
group.channel
CPU TRANSACTIONS
Precise write error (NCNB/Strongly Ordered)
User/Privilege
Precise Abort (CPU)
n/a
Precise read error (NCB/Device or Normal)
User/Privilege
Precise Abort (CPU)
n/a
Imprecise write error (NCB/Device or Normal)
User/Privilege
Imprecise Abort (CPU)
n/a
Undefined Instruction Trap
Illegal instruction
User/Privilege
n/a
(CPU)(1)
MPU access violation
User/Privilege
Abort (CPU)
n/a
SRAM
B0 TCM (even) ECC single error (correctable)
User/Privilege
ESM
1.26
Abort (CPU), ESM =>
B0 TCM (even) ECC double error (non-correctable)
User/Privilege
3.3
nERROR
B0 TCM (even) uncorrectable error (i.e. redundant address
User/Privilege
ESM => NMI => nERROR
2.6
decode)
B0 TCM (even) address bus parity error
User/Privilege
ESM => NMI => nERROR
2.10
B1 TCM (odd) ECC single error (correctable)
User/Privilege
ESM
1.28
Abort (CPU), ESM =>
B1 TCM (odd) ECC double error (non-correctable)
User/Privilege
3.5
nERROR
B1 TCM (odd) uncorrectable error (i.e. redundant address
User/Privilege
ESM => NMI => nERROR
2.8
decode)
B1 TCM (odd) address bus parity error
User/Privilege
ESM => NMI => nERROR
2.12
FLASH
FMC correctable error - Bus1 and Bus2 interfaces (does not
User/Privilege
ESM
1.6
include accesses to EEPROM bank)
FMC uncorrectable error - Bus1 accesses
Abort (CPU), ESM =>
User/Privilege
3.7
(does not include address parity error)
nERROR
FMC uncorrectable error - Bus2 accesses
(does not include address parity error and EEPROM bank
User/Privilege
ESM => nERROR
3.7
accesses)
FMC uncorrectable error - address parity error on Bus1
User/Privilege
ESM => NMI => nERROR
2.4
accesses
FMC correctable error - Accesses to EEPROM bank
User/Privilege
ESM
1.35
FMC uncorrectable error - Accesses to EEPROM bank
User/Privilege
ESM
1.36
DMA TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
User/Privilege
ESM
1.5
response)
External imprecise error on write (Illegal transaction with ok
User/Privilege
ESM
1.13
response)
Memory access permission violation
User/Privilege
ESM
1.2
Memory parity error
User/Privilege
ESM
1.3
DMM TRANSACTIONS
External imprecise error on read (Illegal transaction with ok
User/Privilege
ESM
1.5
response)
External imprecise error on write (Illegal transaction with ok
User/Privilege
ESM
1.13
response)
HTU1
NCNB (Strongly Ordered) transaction with slave error response
User/Privilege
Interrupt => VIM
n/a
External imprecise error (Illegal transaction with ok response)
User/Privilege
Interrupt => VIM
n/a
Memory access permission violation
User/Privilege
ESM
1.9
(1)
The Undefined Instruction TRAP is NOT detectable outside the CPU. The trap is taken only if the instruction reaches the execute stage
of the CPU.
108
System Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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