參數(shù)資料
型號： XRM48L950PGET
廠商： Texas Instruments
文件頁數(shù)： 141/176頁
文件大?。?/td> 0K
描述： MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝： 1
系列： Hercules™ ARM® RM4x
應(yīng)用： 工業(yè)安全，醫(yī)療
核心處理器： ARM? Cortex? - R4F
程序存儲器類型： 閃存（3MB）
控制器系列： RM4
RAM 容量： 256K x 8
接口： CAN，以太網(wǎng)，I²C，LIN，MibSPI，SCI，SPI，USB
輸入/輸出數(shù)： 64
電源電壓： 1.14 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
包裝： 托盤
供應(yīng)商設(shè)備封裝： 144-LQFP（20x20）
其它名稱： 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.6.1.4
External Clock Inputs
The device supports up to two external clock inputs. This clock input must be a square wave input. The
electrical and timing requirements for these clock inputs are specified below. The external clock sources
are not checked for validity. They are assumed valid when enabled.
Table 4-12. External Clock Timing and Electrical Specifications
Parameter
Description
Min
Max
Unit
fEXTCLKx
External clock input frequency
80
MHz
tw(EXTCLKIN)H
EXTCLK high-pulse duration
6
ns
tw(EXTCLKIN)L
EXTCLK low-pulse duration
6
ns
viL(EXTCLKIN)
Low-level input voltage
-0.3
0.8
V
viH(EXTCLKIN)
High-level input voltage
2
VCCIO + 0.3
V
4.6.2
Clock Domains
4.6.2.1
Clock Domain Descriptions
The table below lists the device clock domains and their default clock sources. The table also shows the
system module control register that is used to select an available clock source for each clock domain.
Table 4-13. Clock Domain Descriptions
Clock Domain Name
Default Clock
Clock Source
Description
Source
Selection Register
HCLK
OSCIN
GHVSRC
Is disabled via the CDDISx registers bit 1
Used for all system modules including DMA, ESM
GCLK
OSCIN
GHVSRC
Always the same frequency as HCLK
In phase with HCLK
Is disabled separately from HCLK via the CDDISx registers bit 0
Can be divided by 1up to 8 when running CPU self-test (LBIST)
using the CLKDIV field of the STCCLKDIV register at address
0xFFFFE108
GCLK2
OSCIN
GHVSRC
Always the same frequency as GCLK
2 cycles delayed from GCLK
Is disabled along with GCLK
Gets divided by the same divider setting as that for GCLK when
running CPU self-test (LBIST)
VCLK
OSCIN
GHVSRC
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK via the CDDISx registers bit 2
VCLK2
OSCIN
GHVSRC
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Frequency must be an integer multiple of VCLK frequency
Is disabled separately from HCLK via the CDDISx registers bit 3
VCLK3
OSCIN
GHVSRC
Divided down from HCLK
Can be HCLK/1, HCLK/2, ... or HCLK/16
Is disabled separately from HCLK via the CDDISx registers bit 8
VCLKA1
VCLK
VCLKASRC
Defaults to VCLK as the source
Is disabled via the CDDISx registers bit 4
VCLKA3_S
VCLK
VCLKACON
Defaults to VCLK as the source
Frequency can be as fast as HCLK frequency.
Is disabled via the CDDISx registers bit 10
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
67
Product Folder Links: RM48L950 RM48L750 RM48L550
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XRM48L950ZWTT 功能描述:ARM微控制器 - MCU HERCULES MCU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
XRM48L952PGET 功能描述:ARM微控制器 - MCU 16/32B RISC Fl. MCU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
XRM48L952ZWTT 功能描述:ARM微控制器 - MCU 16/32B RISC Fl. MCU RoHS:否 制造商:STMicroelectronics 核心:ARM Cortex M4F 處理器系列:STM32F373xx 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:72 MHz 程序存儲器大小:256 KB 數(shù)據(jù) RAM 大小:32 KB 片上 ADC:Yes 工作電源電壓:1.65 V to 3.6 V, 2 V to 3.6 V, 2.2 V to 3.6 V 工作溫度范圍:- 40 C to + 85 C 封裝 / 箱體:LQFP-48 安裝風(fēng)格:SMD/SMT
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