參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 152/176頁
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標準包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
Table 4-20. Device Memory Map (continued)
FRAME ADDRESS RANGE
RESPONSE FOR ACCESS TO
FRAME CHIP
FRAME
ACTUA
MODULE NAME
UNIMPLEMENTED LOCATIONS IN
SELECT
SIZE
L SIZE
START
END
FRAME
CoreSight Debug
CSCS0
0xFFA0_0000
0xFFA0_0FFF
4KB
Reads: 0, writes: no effect
ROM
Cortex-R4F
CSCS1
0xFFA0_1000
0xFFA0_1FFF
4KB
Reads: 0, writes: no effect
Debug
ETM-R4
CSCS2
0xFFA0_2000
0xFFA0_2FFF
4KB
Reads: 0, writes: no effect
CoreSight TPIU
CSCS3
0xFFA0_3000
0xFFA0_3FFF
4KB
Reads: 0, writes: no effect
POM
CSCS4
0xFFA0_4000
0xFFA0_4FFF
4KB
Abort
Peripheral Control Registers
HTU1
PS[22]
0xFFF7_A400
0xFFF7_A4FF
256B
Reads: 0, writes: no effect
HTU2
PS[22]
0xFFF7_A500
0xFFF7_A5FF
256B
Reads: 0, writes: no effect
N2HET1
PS[17]
0xFFF7_B800
0xFFF7_B8FF
256B
Reads: 0, writes: no effect
N2HET2
PS[17]
0xFFF7_B900
0xFFF7_B9FF
256B
Reads: 0, writes: no effect
GPIO
PS[16]
0xFFF7_BC00
0xFFF7_BCFF
256B
Reads: 0, writes: no effect
MIBADC1
PS[15]
0xFFF7_C000
0xFFF7_C1FF
512B
Reads: 0, writes: no effect
MIBADC2
PS[15]
0xFFF7_C200
0xFFF7_C3FF
512B
Reads: 0, writes: no effect
I2C
PS[10]
0xFFF7_D400
0xFFF7_D4FF
256B
Reads: 0, writes: no effect
DCAN1
PS[8]
0xFFF7_DC00
0xFFF7_DDFF
512B
Reads: 0, writes: no effect
DCAN2
PS[8]
0xFFF7_DE00
0xFFF7_DFFF
512B
Reads: 0, writes: no effect
DCAN3
PS[7]
0xFFF7_E000
0xFFF7_E1FF
512B
Reads: 0, writes: no effect
LIN
PS[6]
0xFFF7_E400
0xFFF7_E4FF
256B
Reads: 0, writes: no effect
SCI
PS[6]
0xFFF7_E500
0xFFF7_E5FF
256B
Reads: 0, writes: no effect
MibSPI1
PS[2]
0xFFF7_F400
0xFFF7_F5FF
512B
Reads: 0, writes: no effect
SPI2
PS[2]
0xFFF7_F600
0xFFF7_F7FF
512B
Reads: 0, writes: no effect
MibSPI3
PS[1]
0xFFF7_F800
0xFFF7_F9FF
512B
Reads: 0, writes: no effect
SPI4
PS[1]
0xFFF7_FA00
0xFFF7_FBFF
512B
Reads: 0, writes: no effect
MibSPI5
PS[0]
0xFFF7_FC00
0xFFF7_FDFF
512B
Reads: 0, writes: no effect
System Modules Control Registers and Memories
DMA RAM
PPCS0
0xFFF8_0000
0xFFF8_0FFF
4KB
Abort
Wrap around for accesses to
VIM RAM
PPCS2
0xFFF8_2000
0xFFF8_2FFF
4KB
1KB
unimplemented address offsets
between 1kB and 4kB.
RTP RAM
PPCS3
0xFFF8_3000
0xFFF8_3FFF
4KB
Abort
Flash Module
PPCS7
0xFFF8_7000
0xFFF8_7FFF
4KB
Abort
eFuse Controller
PPCS12
0xFFF8_C000
0xFFF8_CFFF
4KB
Abort
Power
Management
PPSE0
0xFFFF_0000
0xFFFF_01FF
512B
Abort
Module (PMM)
Test Controller
PPSE1
0xFFFF_0400
0xFFFF_07FF
1KB
Reads: 0, writes: no effect
(FMTM)
PCR registers
PPS0
0xFFFF_E000
0xFFFF_E0FF
256B
Reads: 0, writes: no effect
System Module -
Frame 2 (see
PPS0
0xFFFF_E100
0xFFFF_E1FF
256B
Reads: 0, writes: no effect
device TRM)
PBIST
PPS1
0xFFFF_E400
0xFFFF_E5FF
512B
Reads: 0, writes: no effect
Generates address error interrupt, if
STC
PPS1
0xFFFF_E600
0xFFFF_E6FF
256B
enabled
IOMM
Multiplexing
PPS2
0xFFFF_EA00
0xFFFF_EBFF
512B
Reads: 0, writes: no effect
Control Module
DCC1
PPS3
0xFFFF_EC00
0xFFFF_ECFF
256B
Reads: 0, writes: no effect
Copyright 2012–2013, Texas Instruments Incorporated
System Information and Electrical Specifications
77
Product Folder Links: RM48L950 RM48L750 RM48L550
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