參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 59/176頁
文件大小: 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
Table 5-23. SPI Master Mode External Timing Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO
= output, and SPISOMI = input)(1)(2)(3)
NO.
Parameter
MIN
MAX
Unit
1
tc(SPC)M
Cycle time, SPICLK (4)
40
256tc(VCLK)
ns
2(5)
tw(SPCH)M
Pulse duration, SPICLK high (clock
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
ns
polarity = 0)
tw(SPCL)M
Pulse duration, SPICLK low (clock
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
3(5)
tw(SPCL)M
Pulse duration, SPICLK low (clock
0.5tc(SPC)M – tf(SPC)M – 3
0.5tc(SPC)M + 3
ns
polarity = 0)
tw(SPCH)M
Pulse duration, SPICLK high (clock
0.5tc(SPC)M – tr(SPC)M – 3
0.5tc(SPC)M + 3
polarity = 1)
4(5)
tv(SIMO-SPCH)M
Valid time, SPICLK high after
0.5tc(SPC)M – 6
ns
SPISIMO data valid (clock polarity =
0)
tv(SIMO-SPCL)M
Valid time, SPICLK low after
0.5tc(SPC)M – 6
SPISIMO data valid (clock polarity =
1)
5(5)
tv(SPCH-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – tr(SPC) – 4
ns
SPICLK high (clock polarity = 0)
tv(SPCL-SIMO)M
Valid time, SPISIMO data valid after
0.5tc(SPC)M – tf(SPC) – 4
SPICLK low (clock polarity = 1)
6(5)
tsu(SOMI-SPCH)M
Setup time, SPISOMI before
tr(SPC) + 2.2
ns
SPICLK high (clock polarity = 0)
tsu(SOMI-SPCL)M
Setup time, SPISOMI before
tf(SPC) + 2.2
SPICLK low (clock polarity = 1)
7(5)
tv(SPCH-SOMI)M
Valid time, SPISOMI data valid after
10
ns
SPICLK high (clock polarity = 0)
tv(SPCL-SOMI)M
Valid time, SPISOMI data valid after
10
SPICLK low (clock polarity = 1)
8(6)
tC2TDELAY
Setup time CS
CSHOLD = 0
0.5*tc(SPC)M +
ns
active until SPICLK
(C2TDELAY+2) * tc(VCLK) -
high (clock polarity =
tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
0)
CSHOLD = 1
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tr(SPC) – 7
tf(SPICS) + tr(SPC) + 5.5
Setup time CS
CSHOLD = 0
0.5*tc(SPC)M +
ns
active until SPICLK
(C2TDELAY+2) * tc(VCLK) -
low (clock polarity =
tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
1)
CSHOLD = 1
0.5*tc(SPC)M +
(C2TDELAY+3) * tc(VCLK) -
tf(SPICS) + tf(SPC) – 7
tf(SPICS) + tf(SPC) + 5.5
9(6)
tT2CDELAY
Hold time SPICLK low until CS
T2CDELAY*tc(VCLK) +
ns
inactive (clock polarity = 0)
tc(VCLK) - tf(SPC) + tr(SPICS) -
tc(VCLK) - tf(SPC) + tr(SPICS) +
7
11
Hold time SPICLK high until CS
T2CDELAY*tc(VCLK) +
ns
inactive (clock polarity = 1)
tc(VCLK) - tr(SPC) + tr(SPICS) -
tc(VCLK) - tr(SPC) + tr(SPICS) +
7
11
10
tSPIENA
SPIENAn Sample Point
(C2TDELAY+1)* tc(VCLK) -
(C2TDELAY+1)*tc(VCLK)
ns
tf(SPICS) – 29
11
tSPIENAW
SPIENAn Sample point from write to
(C2TDELAY+2)*tc(VCLK)
ns
buffer
(1)
The MASTER bit (SPIGCR1.0) is set and the CLOCK PHASE bit (SPIFMTx.16) is set.
(2)
tc(VCLK) = interface clock cycle time = 1 / f(VCLK)
(3)
For rise and fall timings, see the Table 3-5.
(4)
When the SPI is in Master mode, the following must be true:
For PS values from 1 to 255: tc(SPC)M ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)M = 2tc(VCLK) ≥ 40ns.
The external load on the SPICLK pin must be less than 60pF.
(5)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
(6)
C2TDELAY and T2CDELAY is programmed in the SPIDELAY register
Copyright 2012–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
151
Product Folder Links: RM48L950 RM48L750 RM48L550
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