參數(shù)資料
型號： XRM48L950PGET
廠商： Texas Instruments
文件頁數(shù)： 61/176頁
文件大?。?/td> 0K
描述： MCU 16/32Bit FLASH 3MB 144LQFP
標準包裝： 1
系列： Hercules™ ARM® RM4x
應用： 工業(yè)安全，醫(yī)療
核心處理器： ARM? Cortex? - R4F
程序存儲器類型： 閃存（3MB）
控制器系列： RM4
RAM 容量： 256K x 8
接口： CAN，以太網(wǎng)，I²C，LIN，MibSPI，SCI，SPI，USB
輸入/輸出數(shù)： 64
電源電壓： 1.14 V ~ 3.6 V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 144-LQFP
包裝： 托盤
供應商設備封裝： 144-LQFP（20x20）
其它名稱： 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
5.9.5
SPI Slave Mode I/O Timings
Table 5-24. SPI Slave Mode External Timing Parameters (CLOCK PHASE = 0, SPICLK = input, SPISIMO =
input, and SPISOMI = output)(1)(2)(3)(4)
NO.
Parameter
MIN
MAX
Unit
1
tc(SPC)S
Cycle time, SPICLK(5)
40
ns
2(6)
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 0)
14
ns
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 1)
14
3(6)
tw(SPCL)S
Pulse duration, SPICLK low (clock polarity = 0)
14
ns
tw(SPCH)S
Pulse duration, SPICLK high (clock polarity = 1)
14
4(6)
td(SPCH-SOMI)S
Delay time, SPISOMI valid after SPICLK high (clock
trf(SOMI) + 20
ns
polarity = 0)
td(SPCL-SOMI)S
Delay time, SPISOMI valid after SPICLK low (clock polarity
trf(SOMI) + 20
= 1)
5(6)
th(SPCH-SOMI)S
Hold time, SPISOMI data valid after SPICLK high (clock
2
ns
polarity =0)
th(SPCL-SOMI)S
Hold time, SPISOMI data valid after SPICLK low (clock
2
polarity =1)
6(6)
tsu(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK low (clock polarity =
4
ns
0)
tsu(SIMO-SPCH)S
Setup time, SPISIMO before SPICLK high (clock polarity =
4
1)
7(6)
th(SPCL-SIMO)S
Hold time, SPISIMO data valid after SPICLK low (clock
2
ns
polarity = 0)
th(SPCH-SIMO)S
Hold time, SPISIMO data valid after S PICLK high (clock
2
polarity = 1)
8
td(SPCL-SENAH)S
Delay time, SPIENAn high after last SPICLK low (clock
1.5tc(VCLK)
2.5tc(VCLK)+tr(ENAn)+
ns
polarity = 0)
22
td(SPCH-SENAH)S
Delay time, SPIENAn high after last SPICLK high (clock
1.5tc(VCLK)
2.5tc(VCLK)+ tr(ENAn) +
polarity = 1)
22
9
td(SCSL-SENAL)S
Delay time, SPIENAn low after SPICSn low (if new data
tf(ENAn)
tc(VCLK)+tf(ENAn)+27
ns
has been written to the SPI buffer)
(1)
The MASTER bit (SPIGCR1.0) is cleared and the CLOCK PHASE bit (SPIFMTx.16) is cleared.
(2)
If the SPI is in slave mode, the following must be true: tc(SPC)S ≥ (PS + 1) tc(VCLK), where PS = prescale value set in SPIFMTx.[15:8].
(3)
For rise and fall timings, see Table 3-5.
(4)
tc(VCLK) = interface clock cycle time = 1 /f(VCLK)
(5)
When the SPI is in Slave mode, the following must be true:
For PS values from 1 to 255: tc(SPC)S ≥ (PS +1)tc(VCLK) ≥ 40ns, where PS is the prescale value set in the SPIFMTx.[15:8] register bits.
For PS values of 0: tc(SPC)S = 2tc(VCLK) ≥ 40ns.
(6)
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPIFMTx.17).
Copyright 2012–2013, Texas Instruments Incorporated
Peripheral Information and Electrical Specifications
153
Product Folder Links: RM48L950 RM48L750 RM48L550
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