參數(shù)資料
型號(hào): XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 18/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲(chǔ)器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
H
L
H
L
H
L
H
...
128-bitcomparator
H
L
H
L
H
UNLOCK
FlashModuleOutput
OTP Contents
UnlockByScan
Register
InternalTie-Offs
(exampleonly)
(example)
L
H
L
InternalTie-Offs
(exampleonly)
L
H
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.21.6 Advanced JTAG Security Module
This device includes an Advanced JTAG Security Module (AJSM). which provides maximum security to
the device’s memory content by allowing users to secure the device after programming.
Figure 4-21. AJSM Unlock
The device is unsecure by default by virtue of a 128-bit visible unlock code programmed in the OTP
address 0xF0000000.The OTP contents are XOR-ed with the "Unlock By Scan" register contents. The
outputs of these XOR gates are again combined with a set of secret internal tie-offs. The output of this
combinational logic is compared against a secret hard-wired 128-bit value. A match results in the
UNLOCK signal being asserted, so that the device is now unsecure.
A user can secure the device by changing at least one bit in the visible unlock code from 1 to 0. Changing
a 0 to 1 is not possible since the visible unlock code is stored in the One Time Programmable (OTP) flash
region. Also, changing all the 128 bits to zeros is not a valid condition and will permanently secure the
device.
Once secured, a user can unsecure the device by scanning an appropriate value into the "Unlock By
Scan" register of the AJSM module. The value to be scanned is such that the XOR of the OTP contents
and the Unlock-By-Scan register contents results in the original visible unlock code.
The Unlock-By-Scan register is reset only upon asserting power-on reset (nPORRST).
A secure device only permits JTAG accesses to the AJSM scan chain via the Secondary Tap # 2 of the
ICEPick module. All other secondary taps, test taps and the boundary scan interface are not accessible in
this state.
114
System Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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