參數(shù)資料
型號(hào): XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 156/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲(chǔ)器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
4.9.4
POM Overlay Considerations
The POM overlay can map onto up to 8MB of the internal or external memory space. The starting
address and the size of the memory overlay are configurable via the POM module control registers.
Care must be taken to ensure that the overlay is mapped on to available memory.
ECC must be disabled by software via CP15 in case POM overlay is enabled; otherwise ECC errors
will be generated.
POM overlay must not be enabled when the flash and internal RAM memories are swapped via the
MEM SWAP field of the Bus Matrix Module Control Register 1 (BMMCR1).
When POM is used to overlay the flash onto internal or external RAM, there is a bus contention
possibility when another master accesses the TCM flash. This results in a system hang.
The POM module implements a timeout feature to detect this exact scenario. The timeout needs to
be enabled whenever POM overlay is enabled.
The timeout can be enabled by writing 1010 to the Enable TimeOut (ETO) field of the POM Global
Control register (POMGLBCTRL, address = 0xFFA04000).
In case a read request by the POM cannot be completed within 32 HCLK cycles, the timeout (TO)
flag is set in the POM Flag register (POMFLG, address = 0xFFA0400C). Also, an abort is
generated to the CPU. This can be a prefetch abort for an instruction fetch or a data abort for a
data fetch.
The prefetch- and data-abort handlers must be modified to check if the TO flag in the POM module
is set. If so, then the application can assume that the timeout is caused by a bus contention
between the POM transaction and another master accessing the same memory region. The abort
handlers need to clear the TO flag, so that any further aborts are not misinterpreted as having been
caused due to a timeout from the POM.
80
System Information and Electrical Specifications
Copyright 2012–2013, Texas Instruments Incorporated
Product Folder Links: RM48L950 RM48L750 RM48L550
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