參數(shù)資料
型號: XRM48L950PGET
廠商: Texas Instruments
文件頁數(shù): 119/176頁
文件大?。?/td> 0K
描述: MCU 16/32Bit FLASH 3MB 144LQFP
標(biāo)準(zhǔn)包裝: 1
系列: Hercules™ ARM® RM4x
應(yīng)用: 工業(yè)安全,醫(yī)療
核心處理器: ARM? Cortex? - R4F
程序存儲器類型: 閃存(3MB)
控制器系列: RM4
RAM 容量: 256K x 8
接口: CAN,以太網(wǎng),I²C,LIN,MibSPI,SCI,SPI,USB
輸入/輸出數(shù): 64
電源電壓: 1.14 V ~ 3.6 V
工作溫度: -40°C ~ 105°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
包裝: 托盤
供應(yīng)商設(shè)備封裝: 144-LQFP(20x20)
其它名稱: 296-29389
Address Waitstates
Data Waitstates
RAM
Address Waitstates
Data Waitstates
Flash
0MHz
100MHz
0
1
3
0
150MHz
2
150MHz
1
f
HCLK(max)
50MHz
f
HCLK(max)
f
HCLK(max)
f
HCLK(max)
SPNS174A – APRIL 2012 – REVISED SEPTEMBER 2013
3.3
Switching Characteristics over Recommended Operating Conditions for Clock Domains
Table 3-1. Clock Domain Timing Specifications
Parameter
Description
Conditions
Min
Max
Unit
fHCLK
HCLK - System clock frequency
Pipeline mode
200
MHz
enabled
Pipeline mode
50
MHz
disabled
fGCLK
GCLK - CPU clock frequency
fHCLK
MHz
fVCLKA3
VCLKA3 - Primary asynchronous
48
peripheral clock frequency
fVCLKA4
VCLKA4 - Secondary asynchronous
50
MHz
peripheral clock frequency
fRTICLK
RTICLK - clock frequency
fVCLK
MHz
3.4
Wait States Required
Figure 3-1. Wait States Scheme
As shown in the figure above, the TCM RAM can support program and data fetches at full CPU speed without
any address or data wait states required.
The TCM flash can support zero address and data wait states up to a CPU speed of 50MHz in non-pipelined
mode. The flash supports a maximum CPU clock speed of 200MHz in pipelined mode with one address wait
state and three data wait states.
The flash wrapper defaults to non-pipelined mode with zero address wait state and one random-read data wait
state.
Copyright 2012–2013, Texas Instruments Incorporated
Device Operating Conditions
47
Product Folder Links: RM48L950 RM48L750 RM48L550
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