參數(shù)資料
型號(hào): XRT86VL34IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 117/156頁
文件大?。?/td> 816K
代理商: XRT86VL34IB
XRT86VL34
112
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
94: R
X
LOS/CRC I
NTERRUPT
S
TATUS
R
EGISTER
(RLCISR) H
EX
A
DDRESS
: 0
XN
B12
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7-4
-
-
-
Reserved
3
RxLOSINT
RUR/
WC
0
Change in Receive LOS condition Interrupt Status
This bit indicates whether or not the “Change in Receive LOS condi-
tion” interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will
generate an interrupt in response to either one of the following
conditions.
1.
Whenever the Receive T1 Framer block declares the Receive
LOS condition.
2.
Whenever the Receive T1 Framer block clears the Receive
LOS condition.
0 = Indicates that the “Change in Receive LOS Condition” interrupt
has not occurred since the last read of this register.
1 = Indicates that the “Change in Receive LOS Condition” interrupt
has occurred since the last read of this register.
2-0
Reserved
-
-
T
ABLE
95: R
X
LOS/CRC I
NTERRUPT
E
NABLE
R
EGISTER
(RLCIER) H
EX
A
DDRESS
: 0
XN
B13
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
3
RxLOS_ENB
R/W
0
Change in Receive LOS Condition Interrupt Enable
This bit enables the “Change in Receive LOS Condition” interrupt.
0 = Enables “Change in Receive LOS Condition” Interrupt.
1 = Disables “Change in Receive LOS Condition” Interrupt.
2-0
-
-
-
Reserved
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