參數(shù)資料
型號(hào): XRT86VL34IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 134/156頁
文件大?。?/td> 816K
代理商: XRT86VL34IB
XRT86VL34
129
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
3
RxJASEL_n
R/W
0
Receive Jitter Attenuator Enable
This bit permits the user to enable or disable the Jitter Attenuator in
the Receive Path within the XRT86VL34 device.
0 = Disables the Jitter Attenuator to operate in the Receive Path
within the Receive T1 LIU Block.
1 = Enables the Jitter Attenuator to operate in the Receive Path
within the Receive T1 LIU Block.
2
TxJASEL_n
R/W
0
Transmit Jitter Attenuator Enable
This bit permits the user to enable or disable the Jitter Attenuator in
the Transmit Path within the XRT86VL34 device.
0 = Disables the Jitter Attenuator to operate in the Transmit Path
within the Transmit T1 LIU Block.
1 = Enables the Jitter Attenuator to operate in the Transmit Path
within the Transmit T1 LIU Block.
1
JABW_n
R/W
0
Jitter Attenuator Bandwidth Select:
In T1 mode, the Jitter Attenuator Bandwidth is always 3Hz, and this
bit has no effect on the Jitter Attenuator Bandwidth. The FIFOS (bit
D0 of this register) will be used to select the FIFO size, according to
the table below.
0
FIFOS_n
R/W
0
FIFO Size Select:
See table of bit D1 above for the function of this
bit.
T
ABLE
108: LIU C
HANNEL
C
ONTROL
R
EGISTER
1 (LIUCCR1) H
EX
A
DDRESS
: 0
X
0F
N
1
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
0
1
0
1
0
1
0
1
FIFOS_n
bit D0
0
0
1
1
0
0
1
1
JABW
bit D1
T1
T1
T1
T1
E1
E1
E1
E1
Mode
32
64
32
64
32
64
64
64
FIFO
Size
3
3
3
3
10
10
1.5
1.5
JA B-W
Hz
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