參數(shù)資料
型號: XRT86VL34IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 127/156頁
文件大小: 816K
代理商: XRT86VL34IB
XRT86VL34
122
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
102: SS7 S
TATUS
R
EGISTER
FOR
LAPD3 (SS7SR3) H
EX
A
DDRESS
: 0
X
nB28
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
0
SS7_3_STATUS
RUR/
WC
0
SS7 Interrupt Status for LAPD Controller 3
This Reset-Upon-Read bit field indicates whether or not the “SS7”
interrupt has occurred since the last read of this register.
If this interrupt is enabled, then the Receive T1 Framer block will
generate an interrupt when the Received LAPD message is more
than 276 Bytes in length.
0 = Indicates that the “SS7” interrupt has not occurred since the last
read of this register
1 = Indicates that the “SS7” interrupt has occurred since the last
read of this register
T
ABLE
103: SS7 E
NABLE
R
EGISTER
FOR
LAPD3 (SS7ER3) H
EX
A
DDRESS
: 0
XN
B29
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
0
SS7_3_ENB
R/W
0
SS7 Interrupt Enable for LAPD Controller 3
This bit enables or disables the “SS7” interrupt within the LAPD
Controller 3.
If this interrupt is enabled, then the Receive T1 Framer block will
generate an interrupt when the Received LAPD message is more
than 276 Bytes in length.
0 - Disables the “SS7” interrupt within the LAPD Controller 3.
1 - Enables the “SS7” interrupt within the LAPD Controller 3.
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