參數(shù)資料
型號(hào): XRT86VL34IB
廠(chǎng)商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁(yè)數(shù): 94/156頁(yè)
文件大小: 816K
代理商: XRT86VL34IB
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XRT86VL34
89
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
REV. V1.2.0
2
SLIP
RO
0
Slip Buffer Block Interrupt Status
This bit indicates whether or not the Slip Buffer block has any out-
standing interrupt request awaiting service.
0 = Indicates no outstanding Slip Buffer Block interrupt request is
awaiting service
1 = Indicates Slip Buffer block has an interrupt request awaiting ser-
vice. Interrupt Service routine should branch to the interrupt source
and read the Slip Buffer Interrupt Status register (address 0xnB08)
to clear the interrupt
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the Slip Buffer Interrupt Status
Register.
1
ALARM
RO
0
Alarm & Error Block Interrupt Status
This bit indicates whether or not the Alarm & Error Block has any
outstanding interrupt request awaiting service.
0 = Indicates no outstanding interrupt request is awaiting service
1 = Indicates the Alarm & Error Block has an interrupt request await-
ing service. Interrupt service routine should branch to the interrupt
source and read the corresponding alarm and error status registers
(address 0xnB02, 0xnB0E, 0xnB40) to clear the interrupt.
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the corresponding Alarm & Error
Interrupt Status register that generated the interrupt.
0
T1 FRAME
RO
0
T1 Framer Block Interrupt Status
This bit indicates whether or not the T1 Framer block has any out-
standing interrupt request awaiting service.
0 = Indicates no outstanding interrupt request is awaiting service.
1 = Indicates the T1 Framer Block has an interrupt request awaiting
service. Interrupt service routine should branch to the interrupt
source and read the T1 Framer status register (address 0xnB04) to
clear the interrupt
N
OTE
:
This bit will be reset to 0 after the microprocessor has
performed a read to the T1 Framer Interrupt Status register.
T
ABLE
78: B
LOCK
I
NTERRUPT
S
TATUS
R
EGISTER
(BISR) H
EX
A
DDRESS
: 0
X
nB00
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
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