參數(shù)資料
型號: XRT86VL34IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: DATACOM, FRAMER, PBGA225
封裝: 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數(shù): 33/156頁
文件大?。?/td> 816K
代理商: XRT86VL34IB
XRT86VL34
28
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
T
ABLE
12: R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
0
(RSCR 0)
H
EX
A
DDRESS
: 0
X
n10D
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Ch. 0
RUR
0
These bits indicate whether the Channel Associated signaling data,
associated with Time-Slots 0 through 7 within the incoming T1 data-
stream, has changed since the last read of this register, as depicted
below.
0 - CAS data (for Time-slots 0 through 7) has NOT changed since the
last read of this register.
1 - CAS data (for Time-slots 0 through 7) HAS changed since the last
read of this register.
N
OTES
:
This register is only active if the incoming T1 data-stream is
using Channel Associated Signaling.
6
Ch. 1
RUR
0
5
Ch.2
RUR
0
4
Ch.3
RUR
0
3
Ch.4
RUR
0
2
Ch.5
RUR
0
1
Ch.6
RUR
0
0
Ch.7
RUR
0
T
ABLE
13: R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
1
(RSCR 1)
H
EX
A
DDRESS
: 0
X
n10E
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Ch.8
RUR
0
These bits indicate whether the Channel Associated signaling data,
associated with Time-Slots 8 through 15 within the incoming T1 data-
stream, has changed since the last read of this register, as depicted
below.
0 - CAS data (for Time-slots 8 through 15) has NOT changed since the
last read of this register.
1 - CAS data (for Time-slots 8 through 15) HAS changed since the last
read of this register.
This register is only active if the incoming T1 data-stream is using
Channel Associated Signaling.
6
Ch.9
RUR
0
5
Ch.10
RUR
0
4
Ch.11
RUR
0
3
Ch.12
RUR
0
2
Ch.13
RUR
0
1
Ch.14
RUR
0
0
Ch.15
RUR
0
T
ABLE
14: R
ECEIVE
S
IGNALING
C
HANGE
R
EGISTER
2
(RSCR 2)
H
EX
A
DDRESS
: 0
X
n10F
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
7
Ch.16
RUR
0
These bits indicate whether the Channel Associated signaling data, associ-
ated with Time-Slots 16 through 23 within the incoming T1 data-stream, has
changed since the last read of this register, as depicted below.
0 - CAS data (for Time-slots 16 through 23) has NOT changed since the last
read of this register.
1 - CAS data (for Time-slots 16 through 23) HAS changed since the last read
of this register.
N
OTE
:
This register is only active if the incoming T1 data-stream is using
Channel Associated Signaling.
6
Ch.17
RUR
0
5
Ch.18
RUR
0
4
Ch.19
RUR
0
3
Ch.20
RUR
0
2
Ch.21
RUR
0
1
Ch.22
RUR
0
0
Ch.23
RUR
0
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