參數資料
型號： XRT86VL34IB
廠商： EXAR CORP
元件分類： 數字傳輸電路
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： DATACOM, FRAMER, PBGA225
封裝： 19 X 19 MM, 1 MM PITCH, PLASTIC, BGA-225
文件頁數： 73/156頁
文件大?。?/td> 816K
代理商： XRT86VL34IB
XRT86VL34
68
REV. V1.2.0
QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
3-0
TxCond(3:0)
R/W
0000
Transmit Channel Conditioning for Timeslot 0 to 23
These bits allow the user to substitute the input PCM data (Octets 0-23)
with internally generated Conditioning Codes prior to transmission to the
remote terminal equipment on a per-channel basis. The table below pre-
sents the different conditioning codes based on the setting of these bits.
Register address 0xn300 represents time slot 0, and address 0xn317 repre-
sents time slot 23.
T
ABLE
50: T
RANSMIT
C
HANNEL
C
ONTROL
R
EGISTER
0-23 (TCCR 0-23) H
EX
A
DDRESS
: 0
X
n300
TO
0
X
n317
B
IT
F
UNCTION
T
YPE
D
EFAULT
D
ESCRIPTION
-O
PERATION
T
X
C
OND
[1:0]
C
ONDITIONING
C
ODES
0x0 / 0xE
Contents of timeslot octet are unchanged.
0x1
All 8 bits of the selected timeslot octet are inverted (1’s
complement)
OUTPUT = (TIME_SLOT_OCTET) XOR 0xFF
0x2
Even bits of the selected timeslot octet are inverted
OUTPUT = (TIME_SLOT_OCTET) XOR 0xAA
0x3
Odd bits of the selected time slot octet are inverted
OUTPUT = (TIME_SLOT_OCTET) XOR 0x55
0x4
Contents of the selected timeslot octet will be substituted
with the 8 -bit value in the Transmit
Programmable User Code Register (0xn320-0xn337),
0x5
Contents of the timeslot octet will be substituted with the
value 0x7F (BUSY Code)
0x6
Contents of the timeslot octet will be substituted with the
value 0xFF (VACANT Code)
0x7
Contents of the timeslot octet will be substituted with the
BUSY time slot code (111#_####), where ##### is the
Timeslot number
0x8
Contents of the timeslot octet will be substituted with the
MOOF code (0x1A)
0x9
Contents of the timeslot octet will be substituted with the
A-Law Digital Milliwatt pattern
0xA
Contents of the timeslot octet will be substituted with the
μ
-Law Digital Milliwatt pattern
0xB
The MSB (bit 1) of input data is inverted
0xC
All input data except MSB is inverted
0xD
Contents of the timeslot octet will be substituted with the
PRBS X
15
+ X
14
+ 1/QRTS pattern
N
OTE
:
PRBS X
15
+ X
14
+ 1 or QRTS pattern depends on
PRBSType selected in the register 0xn123 - bit 7
0xF
D/E time slot - The TxDE[2:0] bits in the Transmit Signal-
ing and Data Link Select Register (0xn10A) will determine
the data source for D/E time slots.
相關PDF資料
PDF描述
XRT86VL38_2 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
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相關代理商/技術參數
參數描述
XRT86VL34IB-F 功能描述:網絡控制器與處理器 IC 4-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產品:Controller Area Network (CAN) 收發(fā)器數量: 數據速率: 電源電流（最大值）:595 mA 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
XRT86VL38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VL38_07 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VL38_1 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VL38_2 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
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