參數(shù)資料
型號(hào): XRT91L82IB
廠商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁(yè)數(shù): 11/59頁(yè)
文件大?。?/td> 414K
代理商: XRT91L82IB
xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
8
TRANSMITTER SECTION
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
TXDI0P
TXDI0N
TXDI1P
TXDI1N
TXDI2P
TXDI2N
TXDI3P
TXDI3N
TXDI4P
TXDI4N
TXDI5P
TXDI5N
TXDI6P
TXDI6N
TXDI7P
TXDI7N
TXDI8P
TXDI8N
TXDI9P
TXDI9N
TXDI10P
TXDI10N
TXDI11P
TXDI11N
TXDI12P
TXDI12N
TXDI13P
TXDI13N
TXDI14P
TXDI14N
TXDI15P
TXDI15N
LVDS,
LVPECL
Diff and SE
I
P14
P13
N10
N9
N13
N12
M11
M10
M14
M13
L10
L9
L13
L12
K12
K11
J14
K14
J10
K10
J13
J12
H9
J9
H12
H11
G11
G10
F12
G12
G8
G7
Transmit Parallel Data Input
The 155.52 Mbps 16-bit parallel transmit data input should be
applied to the transmit parallel bus simultaneously to be sam-
pled at the rising edge of the TXPCLKIP/N input. The 16-bit
parallel interface is multiplexed into the transmit serial output
interface, MSB first (TXDI15P/N). TXDI[15:0]P/N 100
internal
termination is controlled by INTERM pin or register bit. Inputs
are internally biased to VDD_IO - 1V for AC coupled applica-
tions. For LVPECL Single-Ended applications, either a 100K
VBB bias reference must be provided or the SE_REF pin can
also be used to bias and connected all the negative polarity "N"
pins.
N
OTE
:
The XRT91L82 can accept 166.63 Mbps 16-bit parallel
transmit data input for Forward Error Correction (FEC)
Applications.
TXOP
TXON
CMLDIFF
O
A6
A5
Transmit Serial Data Output
The transmit serial data output stream is generated by multi-
plexing the 16-bit parallel transmit data input into a 2.488 Gbps
serial data output stream. In Forward Error Correction, the
transmit serial data output stream is 2.666 Gbps.
TXSWING
/ INT
LVTTL,
LVCMOS
I/O
D10
Transmit Serial CML Output Swing Mode
Hardware Mode
Selects the generated transmit serial CML
Output swing to the optical module.
"Low" = Low Swing CML Mode
"High" = High Swing CML Mode
This pin is provided with an internal pull-up.
Host Mode
This pin is functions as the microprocessor Inter-
rupt Output.
N
OTE
:
This pin becomes an open drain output in Host Mode
and requires an external pull-up resistor.
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