參數(shù)資料
型號(hào): XRT91L82IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁(yè)數(shù): 28/59頁(yè)
文件大?。?/td> 414K
代理商: XRT91L82IB
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.0.5
25
In Host Mode, the transceiver under the control of the FIFO_AUTORST register bit can automatically recover
from an overflow condition. When the FIFO_AUTORST register bit is set to a "High" level, once an overflow
condition is detected, the chip will set the OVERFLOW pin to a high level and will automatically reset and
center the FIFO. Figure 12 provides a detailed overview of the transmit FIFO in a system interface.
F
IGURE
12. T
RANSMIT
FIFO
AND
S
YSTEM
I
NTERFACE
3.4
It is required that the FIFO_RST pin be pulled "High" for 2 TXPCLKOP/N cycles to flush out the FIFO after the
device is powered on. If the FIFO experiences an Overflow condition, FIFO_RST can be used to manually
reset the FIFO. In Host Mode, the STS-48 transceiver has an automatic FIFO reset register bit that will allow
the FIFO to automatically reset upon an Overflow condition. FIFO_AUTORST register bit should be pulled
"High" to enable the automatic FIFO reset function.
3.5
Transmit Parallel Input to Serial Output (PISO)
The PISO is used to convert 155.52/166.63 Mbps parallel data input to 2.488/2.666 Gbps serial data output
which can interface to an optical module. The PISO bit interleaves parallel data input into a serial bit stream
taking the first bit from TXDI15P/N, then the first bit from TXDI14P/N, and so on as shown in Figure 13.
FIFO Calibration Upon Power Up
F
IGURE
13. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO
Write Pointer
Read Pointer
OVERFLOW
RESET
TXPCLKIP/N
REF1CLKP/N
FIFO Control
Div by
16
2.488/2.666 GHz PLL
CMU
delay
Upstream Device
16 x 9 FIFO
XRT91L82
16
TXDI[15:0]P/N
16
REF2CLKP/N
TXPCLKOP/N
FIFO_AUTORST(Host Mode)
b
0
0
b
0
1
b
0
2
b
0
3
b
0
4
b
0
5
b
0
6
b
0
7
b
n
0
b
n
1
b
n
2
b
n
3
b
n
4
b
n
5
b
n
6
b
n
7
b
n+
0
b
n+
1
b
n+
2
b
n+
3
b
n+
4
b
n+
5
b
n+
6
b
n+
7
b
15
0
b
15
1
b
15
2
b
15
3
b
15
4
b
15
5
b
15
6
b
15
7
16-bit Parallel DIFF Input Data
TXDI0P/N
TXDI15P/N
TXDI
n+
P/N
TXDI
n
P/N
TXOP/N
TXPCLKIP/N
155.52/ 166.63 MHz
2.488/ 2.666 Gbps
b
12
0
b
13
0
b
14
0
b
15
0
b
10
0
b
11
0
b
4
7
b
5
7
b
6
7
b
7
7
b
0
7
b
1
7
b
2
7
b
3
7
P
time (0)
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