
xr
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
XRT91L82
REV. P1.0.5
II
3.6 CLOCK MULTIPLIER UNIT (CMU) AND RE-TIMER ..................................................................................... 26
T
ABLE
10: C
LOCK
M
ULTIPLIER
U
NIT
P
ERFORMANCE
....................................................................................................................... 26
3.7 LOOP TIMING AND CLOCK CONTROL ....................................................................................................... 26
T
ABLE
11: L
OOP
TIMING
AND
REFERENCE
DE
-
JITTER
CONFIGURATIONS
............................................................................................ 27
F
IGURE
14. L
OOP
T
IMING
M
ODE
U
SING
AN
E
XTERNAL
C
LEANUP
VCXO (H
OST
M
ODE
O
NLY
).......................................................... 27
3.8 EXTERNAL LOOP FILTER (HOST MODE ONLY) ........................................................................................ 28
F
IGURE
15. S
IMPLIFIED
D
IAGRAM
OF
THE
E
XTERNAL
L
OOP
F
ILTER
.................................................................................................. 28
3.9 TRANSMIT SERIAL OUTPUT CONTROL ..................................................................................................... 28
F
IGURE
16. T
RANSMIT
S
ERIAL
O
UTPUT
I
NTERFACE
BLOCK
.............................................................................................................. 28
T
ABLE
12: D
IFFERENTIAL
CML O
UTPUT
S
WING
P
ARAMETERS
......................................................................................................... 28
F
IGURE
17. CML D
IFFERENTIAL
V
OLTAGE
S
WING
........................................................................................................................... 29
4.0 DIAGNOSTIC FEATURES ...................................................................................................................30
4.1 SERIAL REMOTE LOOPBACK ..................................................................................................................... 30
F
IGURE
18. S
ERIAL
R
EMOTE
L
OOPBACK
......................................................................................................................................... 30
4.2 PARALLEL REMOTE LOOPBACK (HOST MODE ONLY) ........................................................................... 30
F
IGURE
19. P
ARALLEL
R
EMOTE
L
OOPBACK
.................................................................................................................................... 30
4.3 DIGITAL LOCAL LOOPBACK ....................................................................................................................... 31
F
IGURE
20. D
IGITAL
L
OOPBACK
...................................................................................................................................................... 31
4.4 SONET JITTER REQUIREMENTS ................................................................................................................. 32
4.4.1 JITTER TOLERANCE:................................................................................................................................................ 32
F
IGURE
21. J
ITTER
T
OLERANCE
M
ASK
............................................................................................................................................ 32
F
IGURE
22. XRT91L82 M
EASURED
J
ITTER
T
OLERANCE
IN
LOOP
TIMING
MODE
AT
2.488 G
BPS
STS-48/STM-16 ............................ 33
F
IGURE
23. XRT91L82 M
EASURED
J
ITTER
T
OLERANCE
IN
LOOP
TIMING
MODE
AT
2.666 G
BPS
FEC M
ODE
..................................... 33
4.4.2 JITTER TRANSFER.................................................................................................................................................... 33
F
IGURE
24. XRT91L82 M
EASURED
J
ITTER
T
RANSFER
IN
LOOP
TIMING
MODE
AT
2.488 G
BPS
STS-48/STM-16 .............................. 33
F
IGURE
25. XRT91L82 M
EASURED
J
ITTER
T
RANSFER
IN
LOOP
TIMING
MODE
AT
2.666 G
BPS
FEC M
ODE
....................................... 33
4.4.3 JITTER GENERATION................................................................................................................................................ 34
F
IGURE
26. XRT91L82 M
EASURED
E
LECTRICAL
P
HASE
N
OISE
T
RANSMIT
J
ITTER
G
ENERATION
AT
2.488 G
BPS
.............................. 34
F
IGURE
27. XRT91L82 M
EASURED
E
LECTRICAL
P
HASE
N
OISE
T
RANSMIT
J
ITTER
G
ENERATION
AT
2.666 G
BPS
.............................. 34
5.0 SERIAL MICROPROCESSOR INTERFACE BLOCK .........................................................................35
F
IGURE
28. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................. 35
5.1 SERIAL TIMING INFORMATION ................................................................................................................... 35
F
IGURE
29. T
IMING
D
IAGRAM
FOR
THE
S
ERIAL
M
ICROPROCESSOR
I
NTERFACE
................................................................................ 35
5.2 16-BIT SERIAL DATA INPUT DESCRITPTION ............................................................................................. 36
5.2.1 R/W (SCLK1)............................................................................................................................................................... 36
5.2.2 A[5:0] (SCLK2 - SCLK7)............................................................................................................................................. 36
5.2.3 X (DUMMY BIT SCLK8).............................................................................................................................................. 36
5.2.4 D[7:0] (SCLK9 - SCLK16)........................................................................................................................................... 36
5.3 8-BIT SERIAL DATA OUTPUT DESCRIPTION ............................................................................................. 36
6.0 REGISTER MAP AND BIT DESCRIPTIONS .......................................................................................37
T
ABLE
13: M
ICROPROCESSOR
R
EGISTER
M
AP
................................................................................................................................ 37
T
ABLE
14: M
ICROPROCESSOR
R
EGISTER
0
X
00
H
B
IT
D
ESCRIPTION
................................................................................................. 38
T
ABLE
15: M
ICROPROCESSOR
R
EGISTER
0
X
01
H
B
IT
D
ESCRIPTION
................................................................................................. 39
T
ABLE
16: M
ICROPROCESSOR
R
EGISTER
0
X
02
H
B
IT
D
ESCRIPTION
................................................................................................. 40
T
ABLE
17: M
ICROPROCESSOR
R
EGISTER
0
X
03
H
B
IT
D
ESCRIPTION
................................................................................................. 41
T
ABLE
18: M
ICROPROCESSOR
R
EGISTER
0
X
04
H
B
IT
D
ESCRIPTION
................................................................................................. 42
T
ABLE
19: M
ICROPROCESSOR
R
EGISTER
0
X
05
H
B
IT
D
ESCRIPTION
................................................................................................. 43
T
ABLE
20: M
ICROPROCESSOR
R
EGISTER
0
X
06
H
B
IT
D
ESCRIPTION
................................................................................................. 45
T
ABLE
21: M
ICROPROCESSOR
R
EGISTER
0
X
07
H
B
IT
D
ESCRIPTION
................................................................................................. 46
T
ABLE
22: M
ICROPROCESSOR
R
EGISTER
0
X
3C
H
B
IT
D
ESCRIPTION
................................................................................................. 48
T
ABLE
23: M
ICROPROCESSOR
R
EGISTER
0
X
3D
H
B
IT
D
ESCRIPTION
................................................................................................. 49
T
ABLE
24: M
ICROPROCESSOR
R
EGISTER
0
X
3F
H
B
IT
D
ESCRIPTION
................................................................................................. 49
7.0 ELECTRICAL CHARACTERISTICS ...................................................................................................50
A
BSOLUTE
M
AXIMUM
RATINGS ..................................................................................................................50
ABSOLUTE MAXIMUM POWER AND INPUT LOGIC SIGNALS .............................................................50
POWER AND CURRENT DC E
LECTRICAL
C
HARACTERISTICS
....................................................................50
LVPECL LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS..........................................................51
LVDS LOGIC SIGNAL DC ELECTRICAL CHARACTERISTICS...............................................................51
LVTTL/LVCMOS S
IGNAL
DC ELECTRICAL CHARACTERISTICS ...........................................................52
ORDERING INFORMATION ..................................................................................................................53
196 SHRINK THIN B
ALL
G
RID
A
RRAY
.............................................................................................. 53
(15.0
MM
X
15.0
MM
, STBGA).......................................................................................................... 53