參數(shù)資料
型號(hào)： XRT91L82IB
廠(chǎng)商： EXAR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PBGA196
封裝： 15 X 15 MM, STBGA-196
文件頁(yè)數(shù)： 19/59頁(yè)
文件大?。?/td> 414K
代理商： XRT91L82IB
xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
16
1.0
FUNCTIONAL DESCRIPTION
The XRT91L82 Transceiver is designed to operate with a SONET Framer/ASIC device and provide a high-
speed serial interface to optical networks. The Transceiver converts 16-bit parallel data at 155.52/166.63 MHz
to a serial CML bit stream at 2.488/2.666 Gbps and vice-versa. It implements a clock multiplier unit (CMU),
SONET/SDH serialization/de-serialization (SerDes), and receive clock and data recovery (CDR) unit. The
Transceiver is divided into Transmit and Receive sections and is used to provide the front end component of
SONET equipment, which includes primarily serial transmit and receive functions.
1.1
Hardware Mode vs. Host Mode
Functionality of the STS-48/STM-16 Transceiver can be configured by using either Host mode or Hardware
mode. Hardware mode is selected by pulling HOST/HW "Low" or leaving this pin unconnected. The transceiver
functionality is then controlled by the hardware pins described in the Hardware Pin Descriptions. However, if
Host mode is selected by pulling HOST/HW "High", the functionality is controlled by programming internal R/W
registers using the Serial Microprocessor interface. Whether using Host or Hardware mode, the functionality
remains the same. Therefore, the following sections describe the functionality rather than how each function is
controlled. The Hardware Pin Descriptions and the Register Bit Descriptions concentrate on configuring the
device.
1.2
Clock Input Reference
The XRT91L82 can accept both 155.52 MHz non-FEC or 166.63 MHz FEC clock input at REF1CLKP/N and/or
REF2CLKP/N as its internal timing reference for generating higher speed clocks. The reference clock can be
provided with one of two frequencies chosen by REFREQSEL[1:0]. The reference frequency options for the
XRT91L82 are listed in Table 1.
1.3
In Host mode, the XRT91L82 has the option to accept a lower reference frequency of 77.76 MHz non-FEC or
83.31 MHz FEC clock input at REF1CLKP/N and/or REF2CLKP/N. To use this feature, register bit
ALTFREQSEL must be set "Low" on bit- D5 of ”Configuration Control Register (0x07h)”. The alternate
reference frequency options are listed below in Table 2.
Alternate Clock Input Reference (Host Mode Only)
T
ABLE
1: R
EFERENCE
F
REQUENCY
O
PTIONS
(N
ORMAL
M
ODE
/ FEC
RATE
)
REFREQSEL
[1:0]
CMU R
EFERENCE
C
LOCK
F
REQUENCY
CDR R
EFERENCE
C
LOCK
F
REQUENCY
REF1CLK
C
LOCK
F
REQUENCY
REF2CLK
C
LOCK
F
REQUENCY
T
RANSMIT
D
ATA
R
ATE
R
ECEIVE
D
ATA
R
ATE
00
REF1CLK
REF1CLK
155.52 MHz
non-FEC
not used
2.488 Gbps
non-FEC
2.488 Gbps
non-FEC
01
REF1CLK
REF2CLK
155.52 MHz
non-FEC
166.63 MHz
FEC
2.488 Gbps
non-FEC
2.666 Gbps
FEC
10
REF2CLK
REF1CLK
155.52 MHz
non-FEC
166.63 MHz
FEC
2.666 Gbps
FEC
2.488 Gbps
non-FEC
11
REF2CLK
REF2CLK
not used
166.63 MHz
FEC
2.666 Gbps
FEC
2.666 Gbps
FEC
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