參數(shù)資料
型號(hào)： XRT91L82IB
廠商： EXAR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PBGA196
封裝： 15 X 15 MM, STBGA-196
文件頁(yè)數(shù)： 4/59頁(yè)
文件大小： 414K
代理商： XRT91L82IB
XRT91L82
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
TABLE OF CONTENTS
xr
I
GENERAL DESCRIPTION.................................................................................................1
APPLICATIONS...........................................................................................................................................1
F
IGURE
1. B
LOCK
D
IAGRAM
OF
XRT91L82...................................................................................................................................... 1
FEATURES
......................................................................................................................................................2
PRODUCT ORDERING INFORMATION..................................................................................................2
F
IGURE
2. 196 BGA P
INOUT
OF
THE XRT91L82 (T
OP
V
IEW
).......................................................................................................... 3
T
ABLE
OF
C
ONTENTS
............................................................................................................
I
PIN DESCRIPTIONS ..........................................................................................................4
COMMON
CONTROL
.....................................................................................................................................4
T
RANSMITTER
S
ECTION
..................................................................................................................................8
RECEIVER
SECTION
.......................................................................................................................................11
SERIAL MICROPROCESSOR INTERFACE.............................................................................................14
...................................................................................................................................................................14
JTAG..........................................................................................................................................................15
1.0 FUNCTIONAL DESCRIPTION .............................................................................................................16
1.1 HARDWARE MODE VS. HOST MODE .......................................................................................................... 16
1.2 CLOCK INPUT REFERENCE ......................................................................................................................... 16
T
ABLE
1: R
EFERENCE
F
REQUENCY
O
PTIONS
(N
ORMAL
M
ODE
/ FEC
RATE
)...................................................................................... 16
1.3 ALTERNATE CLOCK INPUT REFERENCE (HOST MODE ONLY) .............................................................. 16
T
ABLE
2: A
LTERNATE
R
EFERENCE
F
REQUENCY
O
PTIONS
(N
ORMAL
M
ODE
/ FEC
RATE
) ................................................................... 17
1.4 DATA LATENCY ............................................................................................................................................. 17
T
ABLE
3: D
ATA
INGRESS
TO
DATA
EGRESS
LATENCY
....................................................................................................................... 17
1.5 FORWARD ERROR CORRECTION (FEC) .................................................................................................... 17
F
IGURE
3. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
F
ORWARD
E
RROR
C
ORRECTION
.................................................................................... 17
1.6 PRBS PATTERN GENERATOR AND ANALYZER ....................................................................................... 17
2.0 RECEIVE SECTION .............................................................................................................................18
2.1 RECEIVE SERIAL INPUT ............................................................................................................................... 18
F
IGURE
4. R
ECEIVE
S
ERIAL
I
NPUT
I
NTERFACE
B
LOCK
..................................................................................................................... 18
T
ABLE
4: D
IFFERENTIAL
CML I
NPUT
S
WING
P
ARAMETERS
.............................................................................................................. 18
2.2 EXTERNAL RECEIVE LOOP FILTER CAPACITORS ................................................................................... 19
F
IGURE
5. E
XTERNAL
L
OOP
F
ILTER
................................................................................................................................................ 19
2.3 RECEIVE CLOCK AND DATA RECOVERY .................................................................................................. 19
T
ABLE
5: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
.......................................................................................................... 20
2.4 EXTERNAL SIGNAL DETECTION ................................................................................................................. 20
T
ABLE
6: LOSD D
ECLARATION
P
OLARITY
S
ETTING
......................................................................................................................... 20
2.5 RECEIVE SERIAL INPUT TO PARALLEL OUTPUT (SIPO) ......................................................................... 21
F
IGURE
6. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
SIPO ........................................................................................................................... 21
2.6 RECEIVE PARALLEL OUTPUT INTERFACE ............................................................................................... 21
F
IGURE
7. R
ECEIVE
P
ARALLEL
O
UTPUT
I
NTERFACE
B
LOCK
............................................................................................................. 21
2.7 RECEIVE PARALLEL INTERFACE LVDS OPERATION .............................................................................. 22
F
IGURE
8. LVDS
EXTERNAL
BIASING
RESISTORS
............................................................................................................................. 22
2.8 PARALLEL RECEIVE DATA OUTPUT DISABLE/MUTE UPON LOSD ........................................................ 22
2.9 PARALLEL RECEIVE CLOCK OUTPUT DISABLE ...................................................................................... 22
2.10 RECEIVE PARALLEL DATA OUTPUT TIMING .......................................................................................... 22
F
IGURE
9. R
ECEIVE
P
ARALLEL
O
UTPUT
T
IMING
.............................................................................................................................. 22
T
ABLE
7: R
ECEIVE
P
ARALLEL
D
ATA
AND
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATIONS
........................................................................... 22
3.0 TRANSMIT SECTION ..........................................................................................................................23
3.1 TRANSMIT PARALLEL INTERFACE ............................................................................................................ 23
F
IGURE
10. T
RANSMIT
P
ARALLEL
I
NPUT
I
NTERFACE
B
LOCK
............................................................................................................. 23
3.2 TRANSMIT PARALLEL DATA INPUT TIMING ............................................................................................. 24
F
IGURE
11. T
RANSMIT
P
ARALLEL
I
NPUT
T
IMING
.............................................................................................................................. 24
T
ABLE
8: T
RANSMIT
P
ARALLEL
D
ATA
AND
C
LOCK
I
NPUT
T
IMING
S
PECIFICATION
............................................................................... 24
T
ABLE
9: T
RANSMIT
P
ARALLEL
C
LOCK
O
UTPUT
T
IMING
S
PECIFICATION
........................................................................................... 24
3.3 TRANSMIT FIFO ............................................................................................................................................. 24
F
IGURE
12. T
RANSMIT
FIFO
AND
S
YSTEM
I
NTERFACE
.................................................................................................................... 25
3.4 FIFO CALIBRATION UPON POWER UP ....................................................................................................... 25
3.5 TRANSMIT PARALLEL INPUT TO SERIAL OUTPUT (PISO) ...................................................................... 25
F
IGURE
13. S
IMPLIFIED
B
LOCK
D
IAGRAM
OF
PISO ......................................................................................................................... 25
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XRT91L82IB-F 功能描述:總線收發(fā)器 Transceiver RoHS:否 制造商:Fairchild Semiconductor 邏輯類(lèi)型:CMOS 邏輯系列:74VCX 每芯片的通道數(shù)量:16 輸入電平:CMOS 輸出電平:CMOS 輸出類(lèi)型:3-State 高電平輸出電流:- 24 mA 低電平輸出電流:24 mA 傳播延遲時(shí)間:6.2 ns 電源電壓-最大:2.7 V, 3.6 V 電源電壓-最小:1.65 V, 2.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-48 封裝:Reel
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XRT94L31_07 制造商:EXAR 制造商全稱:EXAR 功能描述:3-CHANNEL DS3/E3/STS-1 TO STS-3/STM-1 MAPPER IC
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