參數(shù)資料
型號(hào): XRT91L82IB
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁(yè)數(shù): 23/59頁(yè)
文件大?。?/td> 414K
代理商: XRT91L82IB
xr
REV. P1.0.5
PRELIMINARY
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L82
20
T
ABLE
5: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
Jitter specification is defined using a 12kHz to 20MHz appropriate SONET/SDH filter.
1
Required to meet SONET output frequency stability requirements.
2.4
XRT91L82 supports external Signal Detection (SDEXT). The external Signal Detect function is supported by
the SDEXT input. This input is coming from the optical module through an output usually called “SD” or “FLAG”
which indicates the lack or presence of optical power. Depending on the manufacturer of these devices, the
polarity of this signal can be either active "Low" or active "High." The SDEXT and POLARITY inputs are
Exclusive OR’ed to generate the internal Loss of Signal Detect (LOSD) declaration and Mute upon LOSD
control signal. Whenever an external SD is absent, the XRT91L82 will automatically force the receive parallel
data output to a logic state "0" for the entire duration that a LOSD condition is declared as well as update the
status registers whenever the host mode serial microprocessor interface feature is active. This acts as a
receive data mute upon LOSD function to prevent random noise from being misinterpreted as valid incoming
data. Table 6 specifies SDEXT declaration polarity settings.
External Signal Detection
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
45
55
%
REF
TOL
Reference clock frequency tolerance
1
-20
+20
ppm
OCLK
JIT
Clock output jitter generation with 155.52 MHz reference clock
5
7
mUI
rms
OCLK
JIT
Clock output jitter generation with 166.63 MHz reference clock
5
7
mUI
rms
TOL
JIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0.4
0.7
UI
OCLK
FREQ
Frequency output
2.488
2.667
GHz
OCLK
DUTY
Clock output duty cycle
45
55
%
T
ABLE
6: LOSD D
ECLARATION
P
OLARITY
S
ETTING
SDEXT
POLARITY I
NTERNAL
S
IGNAL
D
ETECT
R
ECEIVE
P
ARALLEL
D
ATA
O
UTPUT
RXDO[15:0]P/N
C
LOCK
AND
D
ATA
R
ECOVERY
PLL
R
EFERENCE
L
OCK
0
0
Active Low. Optical signal presence indicated by
SDEXT logic 0 input from optical module.
LOSD not declared.
Not Muted
Hi-Spd Received Data
0
1
Active High. Optical signal presence indicated by
SDEXT logic 1 input from optical module.
LOSD declared.
Muted
Local Reference Clock
1
0
Active Low. Optical signal presence indicated by
SDEXT logic 0 input from optical module.
LOSD declared.
Muted
Local Reference Clock
1
1
Active High. Optical signal presence indicated by
SDEXT logic 1 input from optical module.
LOSD not declared.
Not Muted
Hi-Spd Received Data
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