參數(shù)資料
型號(hào): XRT91L82IB
廠商: EXAR CORP
元件分類(lèi): 數(shù)字傳輸電路
英文描述: 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PBGA196
封裝: 15 X 15 MM, STBGA-196
文件頁(yè)數(shù): 30/59頁(yè)
文件大?。?/td> 414K
代理商: XRT91L82IB
XRT91L82
2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
PRELIMINARY
xr
REV. P1.0.5
27
The on-chip phase/frequency detector can also be used to remove the jitter from a noisy reference signal that
is applied to the REF1CLKP/N or REF2CLKP/N inputs. In this case the LOOPTM_NOJA register bit should be
set "Low," the VCXO_SEL set "High," and the LOOPTM_JA register bit set "Low." In this configuration, the
REF1CLKP/N or REF2CLKP/N CMU reference signal is used as the reference to the de-jitter PLL and the de-
jittered output of the phase locked VCXO is used as the timing reference to the CMU. Table 11 provides
configuration for selecting the loop timing and reference de-jitter modes.
T
ABLE
11: L
OOP
TIMING
AND
REFERENCE
DE
-
JITTER
CONFIGURATIONS
VCXO_SEL
(
REGISTER
BIT
)
LOOPTM_JA
(
REGISTER
BIT
)
LOOPTM_NOJA
(
PIN
/
REGISTER
BIT
)
C
ONFIGURATION
A
CTION
0
0
0
HARDWARE
AND
HOST
MODE
Normal mode
0
0
1
HARDWARE
AND
HOST
MODE
Loop timing without de-jitter VCXO
1
0
0
HOST
MODE
ONLY
REF1CLKP/N or REF2CLKP/N
reference de-jitter VCXO
1
1
0
HOST
MODE
ONLY
Loop timing with de-jitter VCXO
F
IGURE
14. L
OOP
T
IMING
M
ODE
U
SING
AN
E
XTERNAL
C
LEANUP
VCXO (H
OST
M
ODE
O
NLY
)
LOOPTM_JA
RXIP
RXIN
Phase
Detect
CDR
M
Loop Filter
REF1CLKP
REF1CLKN
REF2CLKP
REF2CLKN
VCXO_IN
Div by 16
or 32
Clk
Data
~
~
VCXO
XRT91L82
RXCAP1N/
CPOUT
Serial Microprocessor
2.488/2.666GHz
Retimer
LOOPTM_NOJA
LOCKDET_CMU
REFREQSEL1
REFREQSEL0
M
VCXO_SEL
Charge
Pump
M
1
0
1
0
ALTFREQSEL
PISO
M
0
1
2.488/2.666GHz
CMU
TXOP
TXON
LOOPTM_NOJA
M
HOST/ HW
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