參數(shù)資料
型號： ZL50018GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： 2 K Digital Switch with Enhanced Stratum 3 DPLL
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù)： 19/136頁
文件大?。?/td> 1448K
代理商： ZL50018GAC
ZL50018
Data Sheet
19
Zarlink Semiconductor Inc.
B15
141
ODE
Output Drive Enable (5 V-Tolerant Input with Internal Pull-up)
This is the output enable control for STio0 - 31 and the
output-driven-high control for STOHZ0 - 15. When it is high, STio0
- 31 and STOHZ0 - 15 are enabled. When it is low, STio0 - 31 are
tristated and STOHZ0 - 15 are driven high.
M4, N6, R6,
P7, R7, N7,
M8, N8, P8,
R8, M9, N9,
R9, N10, P9,
R10
16, 18,
20, 22,
23, 24,
25, 26,
27, 28,
30, 32,
34, 36,
37, 38
D0 - 15
Data Bus 0 to 15 (5 V-Tolerant Slew-Rate-Limited Three-state
I/Os)
These pins form the 16-bit data bus of the microprocessor
port.
N12
44
DTA_RDY
Data Transfer Acknowledgment_Ready (5 V-Tolerant
Three-state Output)
This active low output indicates that a data bus transfer is
complete for the Motorola interface. For the Intel interface, it
indicates a transfer is completed when this pin goes from low to
high.
An external pull-up resistor
MUST
hold this pin at HIGH level for
the Motorola mode. An external pull-down resistor
MUST
hold this
pin at LOW level for the Intel mode.
R11
40
CS
Chip Select (5V-Tolerant Input)
Active low input used by the Motorola or Intel microprocessor to
enable the microprocessor port access.
N11
39
R/W_WR
Read/Write_Write (5 V-Tolerant Input)
This input controls the direction of the data bus lines (D0 - 15)
during a microprocessor access. For the Motorola interface, this
pin is set high and low for the read and write access respectively.
For the Intel interface, a write access is indicated when this pin
goes low.
R12
42
DS_RD
Data Strobe_Read (5 V-Tolerant Input)
This active low input works in conjunction with CS to enable the
microprocessor port read and write operations for the Motorola
interface. A read access is indicated when it goes low for the Intel
interface.
K13, K15,
K14, J11,
J12, J13,
J15, H11,
J14, H12,
H13, H15,
G12, G13
82, 84,
86, 87,
88, 89,
90, 91,
92, 93,
94, 96,
98, 99
A0 - 13
Address 0 to 13 (5 V-Tolerant Inputs)
These pins form the 14-bit address bus to the internal memories
and registers.
PBGA Pin
Number
LQFP Pin
Number
Pin Name
Description
相關PDF資料
PDF描述
ZL50018QCC 2 K Digital Switch with Enhanced Stratum 3 DPLL
ZL50019 Enhanced 2 K Digital Switch with Stratum 4E DPLL
ZL50019GAC Enhanced 2 K Digital Switch with Stratum 4E DPLL
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相關代理商/技術參數(shù)
參數(shù)描述
ZL50018GAG2 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA
ZL50018QCC 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256LQFP - Trays
ZL50018QCG1 制造商:Microsemi Corporation 功能描述:PB FREE 2K+ RATE CONVERSION AND S3 DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP
ZL50019 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch with Stratum 4E DPLL
ZL50019_06 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch with Stratum 4E DPLL
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