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參數(shù)資料
| 型號(hào)： | ZL50018GAC |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類： | 路由/交換 |
| 英文描述： | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| 中文描述： | TELECOM, DIGITAL TIME SWITCH, PBGA256 |
| 封裝： | 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256 |
| 文件頁(yè)數(shù)： | 66/136頁(yè) |
| 文件大?。?/td> | 1448K |
| 代理商： | ZL50018GAC |
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ZL50018
Data Sheet
66
Zarlink Semiconductor Inc.
4
SWF
Software Mode Fast Control Bit.
When this bit is low, the SWE bit is high, and the
DPLL is in freerun mode (the FDM1 - 0 bits of the RCCR register are =’11’), the software
slow control mode is enabled. The DPLL outputs will stabilize to delta frequency contents
of Software Delta Frequency Register (SWDFR), after programmed internal DPLL filter
response and phase alignment speed (phase slope) time.
When this bit is high, the SWE bit is high, and the DPLL is in freerun mode, the software
fast control mode is enabled. The DPLL outputs will reach the delta frequency contents
of Software Delta Frequency Register (SWDFR), immediately after writing to the
Software Delta Frequency Register, therefore allowing external software filters and
phase alignment speed (phase slope) limiters to be used. This case will usually require
very frequent updating of the SWDFR register.
When the SWE bit is low or the DPLL is not in freerun mode, this bit is ignored.
3
SWE
Software Mode Enable Bit.
When this bit is low, the Software Delta Frequency Register
(SWDFR) content is ignored and the software mode of the DPLL is disabled. When this
bit is high and the DPLL is in freerun mode, the DPLL software mode is enabled,
meaning that the Software Delta Frequency Register content is used to control the DPLL
output frequency, depending on the value of SWF bit of this register.
When the DPLL is not in freerun mode, this bit is ignored.
2
MRLE
Monitor Register Limits Enable Bit.
When this bit is low, the monitor register content is
ignored and the Stratum 3 default value for each detected reference frequency is used to
set up the DPLL’s reference monitoring functions. When this bit is high, the monitor
registers contents are used to control the monitoring functionality of the device. The
following registers are affected: RnULR, RnLLR, RnMPCRL, RnMPCRU, MPNULRL,
MPNULRU, MPFULRL, MPFULRU, MPNLLRL, MPNLLRU, MPFLLRL, MPFLLRU.
1
RFRE
Reference Frequency Register Enable.
When this bit is low, the reference frequency
value used in the DPLL comes from appropriate reference frequency detector. When this
bit is high, the reference frequency value comes from Reference Frequency Register
(RFR).
0
DPLL_
IRM
DPLL Internal Reset Mode.
When this bit is low, the DPLL module is in the operational
state. When this bit is high, the DPLL module is in the power saving mode. Registers are
not reset and are still accessible in the power saving mode.
Bit
Name
Description
Table 29 - DPLL Control Register (DPLLCR) Bits (continued)
External Read/Write Address: 0040
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
LIN_
RES
SM_
FST
0
SWF
SWE
MRLE
RFRE
DPLL
_IRM
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50018QCC | 2 K Digital Switch with Enhanced Stratum 3 DPLL |
| ZL50019 | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019GAC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019QCC | Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50022 | Enhanced 4 K Digital Switch with Stratum 4E DPLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50018GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256BGA - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA 制造商:Microsemi Corporation 功能描述:IC TDM SWITCH 2K-CH ENH 256PBGA |
| ZL50018QCC | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 2K X 2K 1.8V/3.3V 256LQFP - Trays |
| ZL50018QCG1 | 制造商:Microsemi Corporation 功能描述:PB FREE 2K+ RATE CONVERSION AND S3 DPLL - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TDM SWITCH 2K-CH ENH 256LQFP |
| ZL50019 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch with Stratum 4E DPLL |
| ZL50019_06 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:Enhanced 2 K Digital Switch with Stratum 4E DPLL |
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