參數(shù)資料
型號： ZL50018GAC
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 路由/交換
英文描述： 2 K Digital Switch with Enhanced Stratum 3 DPLL
中文描述： TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝： 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù)： 73/136頁
文件大?。?/td> 1448K
代理商： ZL50018GAC
ZL50018
Data Sheet
73
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 13
Unused
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
12 - 0
SRL12 - 0
Slew Rate Limit Bits:
The binary value of these bits defines the maximum rate of DPLL
phase change (phase slope), where the phase represents difference between the input
reference and output feedback clock. Defined in same units as CFN (unsigned).
Note: The default value is
±
56 ppm (’h099F/CFN = 56 ppm).
Table 38 - Slew Rate Limit Register (SRLR) Bits
Bit
Name
Description
15 - 14
Unused
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
13
BLM
Bypass Limiter Bit:
When this bit is high, the DPLL slew rate limiter is bypassed
(ignored). In combination with FLF_QS, FLC3 - 0, FFL3 - 0 and LPF3 - 0 bits, causes fast
locking of the DPLL output clocks to the selected reference.
When this bit is low, the DPLL performs normal lock following the slew rate limit defined
in the slew rate limit register (SRLR).
12
FLF_QS
Fast Lock Frequency Quick Stabilization Bit:
This bit is used to control speed of
internal frequency stabilization.
When this bit is high, the DPLL internal frequency will quickly stabilize to the appropriate
value, allowing very fast storage of holdover frequency value.
When this bit is low, the internal frequency value will be reached over normal locking time
(i.e. <100 seconds), and some extra jitter on output clocks can be expected.
It is recommended to set this bit if fast locking functionality is desired.
When the BLM bit is low, this bit is ignored.
11 - 8
FLC3 - 0
Fast Lock Control Bits:
Value of these bits (unsigned) control stability of frequency
when FFL3 - 0 bits of this register are used. Larger values result in faster locking and are
recommended for reference clocks with small jitter, while smaller values are
recommended for references with presence of significant jitter.
Table 39 - Bandwidth Control Register (BWCR) Bits
External Read/Write Address: 0049
H
Reset Value: 099F
H
(see Note)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
SRL
12
SRL
11
SRL
10
SRL
9
SRL
8
SRL
7
SRL
6
SRL
5
SRL
4
SRL
3
SRL
2
SRL
1
SRL
0
External Read/Write Address: 004A
H
Reset Value: 0002
H
(see Note)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
BLM
FLF_
QS
FLC
3
FLC
2
FLC
1
FLC
0
FFL
3
FFL
2
FFL
1
FFL
0
LPF
3
LPF
2
LPF
1
LPF
0
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