參數(shù)資料
型號: ZL50018GAC
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 路由/交換
英文描述: 2 K Digital Switch with Enhanced Stratum 3 DPLL
中文描述: TELECOM, DIGITAL TIME SWITCH, PBGA256
封裝: 17 X 17 MM, 1.61 MM HEIGHT, PLASTIC, MS-034, BGA-256
文件頁數(shù): 84/136頁
文件大?。?/td> 1448K
代理商: ZL50018GAC
ZL50018
Data Sheet
84
Zarlink Semiconductor Inc.
Bit
Name
Description
15 - 0
UL[n]15 -
0
(n = 0 - 3)
Reference n Single Period Upper Limit Bits:
The binary value of these bits defines the
upper limit for the period of the REFn input,
minus 1
. The unit of the binary value is
measured in 100 MHz clock periods.
Note 1:
The default value represents limit for 8 kHz input frequency, which is +6.4
μ
s (+10 U I
p-p
of 1.544 MHz).
When the MRLE bit of DPLLCR register is low, these registers are ignored. Depending on reference frequency (detected
or programmed through the Reference Frequency Register), the following values are used instead:
’h2E4A (10UIp-p of 1.544 MHz i.e. 6.4
μ
s) - if reference frequency is 8 kHz
’h002B (0.3UIp-p) - if reference frequency is 1.544 MHz
’h0025 (0.2UIp-p) - if reference frequency is 2.048 MHz
’h0011 (0.2UIp-p) - if reference frequency is 4.096 MHz
’h0007 (0.2UIp-p) - if reference frequency is 8.192 MHz
’h0002 (0.2UIp-p) - if reference frequency is 16.384 MHz
’h0002 (0.2UIp-p) - if reference frequency is 19.44 MHz
Note 2:
Note 3:
The name ‘upper’ is based on frequency.
Table 52 - Upper Limit Register (RnULR) Bits, (n = 0 - 3)
External Read/Write Addresses: 0058
H
, 005C
H
, 0060
H
, 0064
H
Reset Value: 2E4A
H
(see Note 1)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
UL[n]
15
UL[n]
14
UL[n]
13
UL[n]
12
UL[n]
11
UL[n]
10
UL[n]
9
UL[n]
8
UL[n]
7
UL[n]
6
UL[n]
5
UL[n]
4
UL[n]
3
UL[n]
2
UL[n]
1
UL[n]
0
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