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參數(shù)資料
| 型號(hào)： | ZL50031 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| 中文描述： | 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和2度x 2度本地交換 |
| 文件頁(yè)數(shù)： | 18/74頁(yè) |
| 文件大?。?/td> | 765K |
| 代理商： | ZL50031 |
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ZL50031
Data Sheet
18
Zarlink Semiconductor Inc.
If A13 is high, the remaining address input lines are used to select the data and connection memory positions
corresponding to the serial input or output data streams as shown in Table 7 on page 19.
The Control register (CR), the Device Mode Selection register (DMS) and the Block Programming Mode register
(BPM) control all the major functions of the device. The DMS and BPM should be programmed immediately after
system power up to establish the desired switching configuration. The Control register is used to select Data or
Connection Memory for microport operations, ST-BUS output frame and clock modes, and to set Memory Block
Programing and Bit Error Rate Testing.
The Control register (CR) consists of the memory block programming bit (MBP) and the memory select bits (MS2-
0). The memory block programming bit allows users to program the entire connection memory in two frames (See
Section 8.0, “Memory Block Programming“ on page 16). The memory select bits control the selection of the
connection memories or the data memories. See Table 8 on page 35 for contents of the Control register.
The DMS register consists of the backplane and the local mode selection bits (BMS, LG31 - LG30, LG21 - LG20,
LG11 - LG10 and LG01 - LG00) that are used to enable various switching modes for the backplane and the local
interfaces respectively. See Table 9 on page 36 for the content of the DMS register.
The BPM register consists of the block programming data bits (LBPD2-0 and BBPD2-0) and the block programming
enable bit (BPE). The block programming enable bit allows users to program the entire backplane and local
connection memories in two frames (see section 8.0, “Memory Block Programming“ on page 16). If the ODE pin is
low, the backplane CT-Bus is in input mode and the local output drivers are in high impedance state. If the ODE pin
0008
H
0009
H
Local Input Bit Delay Register 4, LIDR4
Local Input Bit Delay Register 5, LIDR5
000A
H
to 001B
H
001C
H
Reserved
Backplane Output Advancement Register 0, BOAR0
001D
H
Backplane Output Advancement Register 1, BOAR1
001E
H
001F
H
0020
H
Backplane Output Advancement Register 2, BOAR2
Backplane Output Advancement Register 3, BOAR3
Local Output Advancement Register 0, LOAR0
0021
H
0022
H
to 0026
H
0027
H
0028
H
0029
H
Local Output Advancement Register 1, LOAR1
Reserved
Local BER Input Selection Register, LBIS
Local BER Register, LBERR
Backplane BER Input Selection Register, BBIS
002A
H
Backplane BER Register, BBERR
002B
H
002C
H
002D
H
DPLL Operation Mode Register 1, DOM1
DPLL Operation Mode Register 2, DOM2
DPLL Output Adjustment Register, DPOA
002E
H
DPLL House Keeping Register, DHKR
A13 - A0
Location
Table 6 - Address Map For Internal Registers (A13 = 0) (continued)
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|---|---|
| ZL50031QEG1 | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP |
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| ZL50050GAC | 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL, RATE CONV & 32 I/O - Trays |
| ZL50050GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 1.8V/3.3V 196BGA - Trays 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL RATE CONV & 32 I/O 制造商:Microsemi 功能描述:SWIT FABRIC 8KX8K/4K X 4K 1.8V/3.3V 196BGA |
| ZL50051 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
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