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參數(shù)資料
| 型號(hào)： | ZL50031 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| 中文描述： | 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和2度x 2度本地交換 |
| 文件頁數(shù)： | 50/74頁 |
| 文件大?。?/td> | 765K |
| 代理商： | ZL50031 |
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ZL50031
Data Sheet
50
Zarlink Semiconductor Inc.
Bit
15 - 9
Name
POS6 - 0
Description
Phase Offset Bits:
These seven bits refer to the 2’s complement phase word to
control the DPLL output phase offset. The offset varies in steps of 15 ns if the
reference is 8 kHz or 2.048 MHz. The offset varies in steps of 20 ns if the reference
is 1.544 MHz.
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
Skew Control Bits:
These three bits control the delay of the DPLL outputs from 0
to 7 steps in delay intervals of 3.5 ns.
8 - 3
2 - 0
Unused
SKC2 - 0
Table 22 - DPLL Output Adjustment (DPOA) Register Bits
Bit
15 - 7
6
Name
Unused
SLS
Description
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
Secondary Loss Detection Bit (Read-only bit):
When the secondary reference fails,
this bit is set to high.
Primary Loss Detection Bit (Read-only bit):
When the primary reference fails, this bit
is set to high.
DPLL Output Clock Bit:
When high, the primary output C32/64o is 65.536 MHz clock.
When low, the primary output C32/64o is 32.768 MHz clock. This is the only writable bit
in this register.
Limit (Read-only bit):
Indicates that DPLL Phase Slope Limiter limits input phase.
State:
These 3 bits indicate the state of the DPLL State Machine. Please refer to Figure
7, "State Machine Diagram" on page 25.
5
PLS
4
CKM
3
Limit
State 2-0
2 - 0
Table 23 - DPLL House Keeping (DHKR) Register Bits
Read/Write Address: 002D
H
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
POS
6
POS
5
POS
4
POS
3
POS
2
POS
1
POS
0
0
0
0
0
0
0
SKC2
SKC1
SKC0
Read/Write Address: 002E
H
for DHKR Register
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
SLS
PLS
CKM
Limit
State2
State1
State0
State 2-0
State Name
000
NORMAL_PRI
001
Reserved
010
HOLDOVER_PRI
011
MTIE_PRI
100
NORMAL_SEC
101
Reserved
110
HOLDOVER_SEC
111
MTIE_SEC
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| ZL50051 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
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