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參數(shù)資料
| 型號： | ZL50031 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| 中文描述： | 靈活的為4 K × 2鉀通道數(shù)字交換機的H.110接口和2度x 2度本地交換 |
| 文件頁數(shù)： | 57/74頁 |
| 文件大小： | 765K |
| 代理商： | ZL50031 |
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ZL50031
Data Sheet
57
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
AC Electrical Characteristics
- Output Frame Pulse and Output Clock Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
Backplane Frame Boundary Offset
tFBOS
t
CFPOW
-6.25
10
ns
2
FRAME_A_io, FRAME_B_io Output Pulse
Width
114.5
122
129.5
ns
C
L
=30 pF
3
Delay from FRAME_A_io, FRAME_B_io
output falling edge to C8_a_io,C8_B_io
output rising edge
t
CFODF
57.25
64.75
ns
4
Delay from C8_A_io,C8_B_io output rising
edge to FRAME_A_io,FRAME_B_io output
rising edge
t
CFODR
57.25
64.75
ns
5
C8_A_io, C8_B_io Output Clock Period
t
C8MP
t
C8MH
t
C8ML
t
rC8o
t
fC8o
t
C32MOD
t
C32MP
t
C32MH
t
C32ML
t
C64MP
t
C64MH
t
C64ML
t
r32o
114.5
122
129.5
ns
C
L
=30 pF
6
C8_A_io, C8_B_io Output High Time
57.25
64.75
ns
7
C8_A_io, C8_B_io Output Low Time
57.25
64.75
ns
8
C8_A_io, C8_B_io Output Rise Time
13
ns
9
C8_A_io, C8_B_io Output Fall Time
14
10
C32/64o (32.768 MHz) Output Delay Time
7.5
ns
C
L
=30 pF
11
C32/64o (32.768 MHz) Period
23
30.5
38
ns
12
C32/64o (32.768 MHz) High Time
11.5
19
ns
13
C32/64o (32.768 MHz) Low Time
11.5
19
ns
14
C32/64o (65.536 MHz) Period
11.5
19
ns
15
C32/64o (65.536 MHz) High Time
6.5
8
ns
16
C32/64o (65.536 MHz) Low Time
6.5
13
ns
17
C32/64o Clock Rise Time
(32.768 MHz or 65.536 MHz)
5
ns
18
C32/64o Clock Fall Time
(32.768 MHz or 65.536 MHz)
t
f32o
6
ns
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| ZL50051 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
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