- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄373785 > ZL50031 (Zarlink Semiconductor Inc.) Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch PDF資料下載
參數(shù)資料
| 型號(hào)： | ZL50031 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| 中文描述： | 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和2度x 2度本地交換 |
| 文件頁(yè)數(shù)： | 38/74頁(yè) |
| 文件大?。?/td> | 765K |
| 代理商： | ZL50031 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)當(dāng)前第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)
ZL50031
Data Sheet
38
Zarlink Semiconductor Inc.
8-6
BBPD2-0
Backplane Block Programming Data Bits:
These bits carry the value to be loaded into
the backplane connection memory block whenever the Memory Block Programming feature
is activated. After the MBP bit in the Control Register is set to high and the BPE is set to
high, the contents of the bits BBPD2 - 0 are loaded into bits 15 - 13 of the backplane
connection memory. Bits 12 - 0 of the backplane connection memory are programmed to be
zero.
5-3
LBPD2-0
Local Block Programming Data Bits:
These bits carry the value to be loaded into the
local connection memory whenever the Memory Block Programming feature is activated.
After the MBP bit in the Control Register is set to high and the BPE is set to high, the
contents of the bits LBPD2 - 0 are loaded into bits 15 - 13 of the local connection memory.
Bits 12 - 0 of the local connection memory are programmed to be zero.
2
BPE
Block Programming Enable:
A low to high transition of this bit enables the Memory Block
Programming function. The BPE, BBPD2-0 and LBPD2-0 in the BPM register must be
defined in the same write operation. Once the BPE bit is set to high, ZL50031 requires two
frames to complete the block programming. After the block programming has finished, the
BPE bit returns to low to indicate that the operation is complete. When BPE is high, BPE or
MBP can be set to low to abort the programming operation. When BPE is high, the other
bits in the BPM register must not be changed for two frames to ensure proper operation.
Whenever the microprocessor writes BPE to be high to start the block programming
function, the user must maintain the same logical value on the other bits in the BPM register
to avoid any change in the setting of the device.
1-0
Unused
Reserved.
In normal functional mode, these bits
MUST
be set to zero.
Bit
Name
Description
Table 10 - Block Programming Mode (BPM) Register Bits (continued)
Read/Write Addresses:
0004
H
for LIDR0 register,
0006
H
for LIDR2 register,
0008
H
for LIDR4 register,
0005
H
for LIDR1 register,
0007
H
for LIDR3 register,
0009
H
for LIDR5 register,
Reset Value: 0000
H
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
LIDR0 0
LID24
LID23
LID22
LID21
LID20
LID14
LID13
LID12
LID11
LID10
LID04
LID03
LID02
LID01
LID00
LIDR1 0
LID54
LID53
LID52
LID51
LID50
LID44
LID43
LID42
LID41
LID40
LID34
LID33
LID32
LID31
LID30
LIDR2 0
LID84
LID83
LID82
LID81
LID80
LID74
LID73
LID72
LID71
LID70
LID64
LID63
LID62
LID61
LID60
LIDR3 0
LID114
LID113
LID112
LID111
LID110
LID104
LID103
LID102
LID101
LID100
LID94
LID93
LID92
LID91
LID90
LIDR4 0
LID144
LID143
LID142
LID141
LID140
LID134
LID133
LID132
LID131
LID130
LID124
LID123
LID122
LID121
LID120
LIDR5 0
0
0
0
0
0
0
0
0
0
0
LID154
LID153
LID152
LID151
LID150
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50031QEG1 | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50053QCC | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50051 | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50051GAC | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50073GAC | 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50031QEG1 | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP |
| ZL50050 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs |
| ZL50050GAC | 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL, RATE CONV & 32 I/O - Trays |
| ZL50050GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 1.8V/3.3V 196BGA - Trays 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL RATE CONV & 32 I/O 制造商:Microsemi 功能描述:SWIT FABRIC 8KX8K/4K X 4K 1.8V/3.3V 196BGA |
| ZL50051 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。