參數(shù)資料
型號(hào): ZL50031
廠商: Zarlink Semiconductor Inc.
英文描述: Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch
中文描述: 靈活的為4 K × 2鉀通道數(shù)字交換機(jī)的H.110接口和2度x 2度本地交換
文件頁數(shù): 48/74頁
文件大?。?/td> 765K
代理商: ZL50031
ZL50031
Data Sheet
48
Zarlink Semiconductor Inc.
4 -3
DIV1 - 0
Divider Bits:
These two bits define the relationship between the input reference
and the NREFo output.
2
Reserved
Reserved.
In normal functional mode, this bit
MUST
be set to zero.
1- 0
CNS1 - 0
NREFo Source Selection Bits:
These three bits select three of the LREF3 -
LREF0 to be the NREFo source.
Bit
Name
Description
Table 20 - DPLL Operation Mode (DOM2) Register Bits (continued)
DIV1
DIV0
NREFo Output
0
0
Input reference
0
1
Input reference/193 (8 kHz signal when input reference
clock = 1.544 MHz)
1
0
Input reference/256 (8 kHz signal when input reference
clock = 2.048 MHz)
1
1
Reserved
CNS1
CNS0
NREFo Source
0
0
LREF0
0
1
LREF1
1
0
LREF2
1
1
LREF3
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