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參數(shù)資料
| 型號： | ZL50031 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| 中文描述： | 靈活的為4 K × 2鉀通道數(shù)字交換機的H.110接口和2度x 2度本地交換 |
| 文件頁數(shù)： | 60/74頁 |
| 文件大?。?/td> | 765K |
| 代理商： | ZL50031 |
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ZL50031
Data Sheet
60
Zarlink Semiconductor Inc.
Characteristics are over recommended operating conditions unless otherwise stated.
Typical figures are at 25
°
C and are for design aid only: not guaranteed and not subject to production testing.
Figure 21 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
Figure 22 - Reference Output Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
Figure 23 - Reference Input Timing Diagram when (DIV1, DIV0) = (0, 0) in DOM2 Register
Figure 24 - Reference Output Timing Diagram when (DIV1, DIV0) = (1, 0) in DOM2 Register
AC Electrical Characteristics
- Reference Output Timing
Characteristic
Sym.
Min.
Typ.
Max.
Units
Notes
1
2
3
4
5
NREFo Output Delay Time
NREFo Clock Period
NREFo Clock High Time
NREFo Clock Low Time
NREFo Clock Rise/Fall Time
t
ROD
t
RP
t
RH
t
RL
t
rREF
,
t
fREF
t
R8KOP
t
R8KO2H
t
R8KO2L
t
R8KO15H
t
R8KO15L
20
ns
(DIV1,DIV0) =
(0,0)
in the DOM2
Register
Same as LREF0-3 Period
Same as LREF0-3 High Time
Same as LREF0-3 Low Time
0
12
14
ns
6
7
8
9
10 NREFo Clock Low Time
NREFo Clock Period
NREFo Clock High Time
NREFo Clock Low Time
NREFo Clock High Time
124.9
124.4
480.5
124.3
640.5
125
124.5
488
124.4
648
125.1
124.6
495.5
124.5
655.5
μ
s
μ
s
ns
μ
s
ns
(DIV1,DIV0) =
(0,1) or
(DIV1,DIV0) =
(1,0)
in the DOM2
Register
LREF0-3
(8 kHz)
t
fREF
t
rREF
NREFo
(8 kHz)
t
RL
t
RP
t
t
ROD
LREF0-3
(2.048 MHz)
t
fREF
t
rREF
t
RP
NREFo
(2.048 MHz)
t
RL
t
RH
t
ROD
LREF0-3
(1.544 MHz)
t
fREF
t
rREF
t
RP
t
RL
t
RH
t
ROD
NREFo
(1.544 MHz)
LREF0-3
(2.048 MHz)
NREFo
(8 kHz)
t
R8KO2H
t
R8KO2L
t
R8KOP
t
ROD
t
fREF
t
rREF
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