- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373785 > ZL50031 (Zarlink Semiconductor Inc.) Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch PDF資料下載
參數(shù)資料
| 型號： | ZL50031 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| 中文描述： | 靈活的為4 K × 2鉀通道數(shù)字交換機的H.110接口和2度x 2度本地交換 |
| 文件頁數(shù)： | 34/74頁 |
| 文件大?。?/td> | 765K |
| 代理商： | ZL50031 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁當(dāng)前第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁
ZL50031
Data Sheet
34
Zarlink Semiconductor Inc.
20.0 JTAG Support
The ZL50031 JTAG interface conforms to the Boundary-Scan IEEE1149.1 standard. The operation of the
boundary-scan circuitry is controlled by an external Test Access Port (TAP) Controller.
20.1 Test Access Port (TAP)
The Test Access Port (TAP) accesses the ZL50031 test functions. It consists of three input pins and one output pin
as follows:
Test Clock Input (TCK)
- TCK provides the clock for the test logic. The TCK does not interfere with any on-
chip clock and thus remains independent in the functional mode. The TCK permits shifting of test data into or
out of the Boundary-Scan register cells concurrently with the operation of the device and without interfering
with the on-chip logic.
Test Mode Select Input (TMS)
- The TAP Controller uses the logic signals received at the TMS input to
control test operations. The TMS signals are sampled at the rising edge of the TCK pulse. This pin is
internally pulled to Vdd when it is not driven from an external source.
Test Data Input (TDi)
- Serial input data applied to this port is fed either into the instruction register or into a
test data register, depending on the sequence previously applied to the TMS input. Both registers are
described in a subsequent section. The received input data is sampled at the rising edge of TCK pulses.
This pin is internally pulled to Vdd when it is not driven from an external source.
Test Data Output (TDo)
- Depending on the sequence previously applied to the TMS input, the contents of
either the instruction register or data register are serially shifted out towards the TDo. The data out of the
TDO is clocked on the falling edge of the TCK pulses. When no data is shifted through the boundary scan
cells, the TDO driver is set to a high impedance state.
Test Reset (TRST
) - Resets the JTAG scan structure. This pin is internally pulled to Vdd when it is not driven
from an external source. An external pull-down resistor is required on this pin so that the ZL50031 will not enter
the JTAG test mode during power up.
20.2 Instruction Register
The ZL50031 uses the public instructions defined in the IEEE 1149.1 standard. The JTAG Interface contains a four-
bit instruction register. Instructions are serially loaded into the instruction register from TDi when the TAP Controller
is in its shifted-IR state. These instructions are subsequently decoded to achieve two basic functions: to select the
test data register that may operate while the instruction is current and to define the serial test data register path that
is used to shift data between TDi and TDo during data register scanning.
20.3 Test Data Register
As specified in IEEE 1149.1, the ZL50031 JTAG interface contains three test data registers:
The Boundary-Scan Register
- The Boundary-Scan register consists of a series of Boundary-Scan cells
arranged to form a scan path around the boundary of the ZL50031 core logic.
The Bypass Register
- The Bypass register is a single stage shift register that provides a one-bit path from
TDi to TDo.
The Device Identification Register
- The JTAG device ID for the ZL50031 is 0086614B
H
.
Version<31:28>:0000
Part No. <27:12>:0000 1000 0110 0110
Manufacturer ID<11:1>: 0001 0100 101
LSB<0>:1
20.4 BSDL
A BSDL (Boundary Scan Description Language) file is available from Zarlink Semiconductor to aid in the use of the
IEEE 1149.1 test interface.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ZL50031QEG1 | Flexible 4 K x 2 K Channel Digital Switch with H.110 Interface and 2 K x 2 K Local Switch |
| ZL50053QCC | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50051 | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50051GAC | 8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
| ZL50073GAC | 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ZL50031QEG1 | 制造商:Microsemi Corporation 功能描述:FLEXIBLE 4 K X 2 K CH DGTL SWIT W/ H.110 INTRFC AND 1 K X 1 - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP 制造商:Microsemi Corporation 功能描述:IC DGTL SWITCH 4K X 2K 256MQFP |
| ZL50050 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K-Channel Digital Switch with High Jitter Tolerance, Per Stream Rate Conversion (2, 4, 8, 16, or 32 Mbps), and 32 Inputs and 32 Outputs |
| ZL50050GAC | 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL, RATE CONV & 32 I/O - Trays |
| ZL50050GAG2 | 制造商:Microsemi Corporation 功能描述:SWIT FABRIC 8KX8K/4K X 4K 1.8V/3.3V 196BGA - Trays 制造商:Microsemi Corporation 功能描述:8K DX HI JIT TOL RATE CONV & 32 I/O 制造商:Microsemi 功能描述:SWIT FABRIC 8KX8K/4K X 4K 1.8V/3.3V 196BGA |
| ZL50051 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:8 K Channel Digital Switch with High Jitter Tolerance, Single Rate (8 or 16 Mbps), and 64 Inputs and 64 Outputs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。